WAT-Introduction.ppt

PIE B3 WATXinguang Sun2007 03 31 WATIntroduction Outline WhyWAT Hardware SoftwareSystemTester Probe ProbeCardTestPatternandMeasurementWATWATCHsystemWATTestItems WhatisWAT WaferAcceptanceTest Whatkindofwork Anelectricaltestsystem non productivityactivityWATisanelectricaltestsystemforprocessgoodnessmonitor Devicecharacteristics resistor capacitor interconnection continuity spacing insulation leakage WATistheprimaryqualityelementforafoundryFAB thequalityassuranceforwaferoutput WATcharacteristics DCforceandmeasurement Automation highthroughput precision sampling ThepurposeofWAT MonitorProcessWindow CheckDesignRule ControltheProcessParameters SPC DebugtheProcessError ReliabilityCharacterization DeviceModelingforCircuitDesign DevelopnextGeneration Toolintroduction Tester KeithleyS630 Agilent4072A KeithleyCabinet Keithleytesterhead AgilentCabinet Agilenttesterhead Forcevoltage current Measurevoltage current Capacitancemeasure ControlprobermovingAswitchmatrixtoprovide48pinoutput KeithleyS600Hardware PAA S600SystemCabinet Agilent4072Hardware SystemCabinet Testhead OpticalInterface S630v s Agilent4072Hardware S630v s Agilent4072Software AgilentSemiconductorProcessEvaluationCoreSoftware KeithleyKeithleyTestEnvironment Toolintroduction Prober Waferload unloadProbecardwaferpre alignment precisealignment Movewafer controlledbytesterWafer probecardcontact TSKUF200 TELP8 XL Toolintroduction ProbeCard Tester waferinterface Connecttestinstrumenttoteststructureonwafer ForAgilenttester ForKeithleytester Vendor NANO JEM MJCJEM K S ProbeCard EpoxyType HigherleakageMoretouchdowntimesEasytomake ProbeCard BladeType LowerleakageLesstouchdowntimesDifficulttomake SmartProbeCards ProbeCard EEPROMChip Remembers 1 ProbeCardID2 NumberofTouchdowns3 OtherInfo DoesNotConsumeTesterPins ProbeCardsMaterial Cuissofterandcanbeusedforin lineWATtest Toolintroduction System TestPatternandMeasurement TestPattern Testkey Usuallyinsidechip fordesignrulecheck yieldmonitorandprocessqualificationanddevelopment Canchecksubgroundrule Testline Usuallyonscribeline Thesepatternwillbedestroyedafterdiesaw ForproductionmonitorSMIC0 13umStandard1X22PadArray 70um 70um 190um Testconditionexample TestconditionisprovidebyPIE HowtoapplyWATrecipesetuprequest HomewebApplicationEntryOperationsWATworkrequessystem Fornewrecipesetuprequest Forrecipechange WATtestlinecoordinateswitch 0degree X xY y90degree X yY x180degree X xY y270degree X yY x 0degree 90degree 180degree 270degree PCMSpec PCM processcontrolmonitor LCMO13GE B 31 1P7M6C02 5ID NAME UNIT SL SH failsite InkL InkH InkSite11002 VTI N12 10 D13 V 0 29 0 39 3 11007 IDSAT N12 10 D13 mA UM 0 455 0 615 3 11012 IOFF N12 10 D13 pA UM 0 3000 3 11016 BVDS N12 10 D13 V 2 8 12 3 LottypeisE1 E2 E3 MproductneedPCMspec PCMSpecissueflow 1 IssueFECP NewcreateClass C ModifyClass A 2 IssueECN AttachPCMspecfile PCMSpecexample WATAcceptanceCriteria WATsamplingruleWATtesteverywafer WATtest5sitesperwafer WATtesteachcriticalitemineachtestingsite WATFailDefinationItemFail Ifthereisatestparameteroutofproductspecification thenthisitemfail SiteFail Ifthereisoneormoreitemsfailureofonesite thenthissitefail WaferFail IftherearethreeormoresitesfailureofoneWafer thenthiswaferfail WATAcceptanceRuleWATwillnotacceptthreeormoreSiteFailwafer WATwillaccepttwoorlessSiteFailwafer WATfailwaferdispositionwillfollowWATAbnormalDispositionProcedureWATacceptedwaferwilltransporttothenextstep Watchsystem WATCHSystemisonesub systemoftheMy EDAsystem ThesystempurposeistoprovideuserstosetuptheWATCHrulesanddefinespecifications thenthesystemwillcheckthewafers WATdatatopreventbadwafersandprocesses TowatchiftheWATdataisoutofSPEC TojudgeifthedataoutofDHorPHrules SendE mailautomaticallytoinformlotownerlotdatainformation warningorhold Watchsystemsetup Watchmail WatchRule DH DefaultDefinedRule 5 ruletypeDHRule1 1 WaferPass FailCheck Ifanykeyparameterinonesitefail thesitefail CriteriaIfthefailuresiteswithingreaterorequalthan3 thewaferisfail Scarp Retestcriteria 2 LotHold ReleaseCheck Ifthewaferfailpcsfrom 1 1 HoldDHRule2 Forkeyparameterlike VBD or Vbd Anysitefailwithinwafer HoldDHRule3 AnykeyparameterOOSandOOVsiterate 10 thenthislotfail DHRule4 Anysitewholeparameterfailrate 25 thenthislotfail DHRule5 ForkeyparameterscountinrawdataissamewithlimitfileDHRule6 Forkeyparametersandsitescountinlastrawdataissamewithpreviousdataperwafer WatchRule PH PARAMETERHOLDRule Userdefine PHRule1 X 5 Bywafer Foreachparameterdatayouselect iffailsitenumberofeachwaferislargerthanorequaltotX Rule1checkfail PHRule2 X 125 ByLot Foreachparameterdatayouselect iffailsitenumberofthewholelotislargerthanorequaltotX Rule2checkfail PHRule3 X 25 BySite Foreachparameterdatayouselect iffailsitenumberofthewholelotislargerthanorequaltotX Rule3checkfail Mostly TheWATParameterNamingUseThisType IfNeed Sample UseLogicDeviceWAT11VTITestItemsassample WATParameterNamingRule 1 MOSFETTransistor sNaming WATParameterNamingRule 2 MOSFETCapacitor WATParameterNamingRule 3 FieldTransistor 4 JunctionDiode WATParameterNamingRule 5 Sheetresistance WATParameterNamingRule 6 Contact via stackvia resistance WATParameterNamingRule 7 Poly metalcontinuity 8 SalicideBridge WATParameterNamingRule 9 Intra Isolation 10 Inter Isolation WATParameterNamingRule 11 PIP MIMandmetalinterconnectcapacitors 12 VerticalBipolar WATParameterNamingRule 1 NMOS sVTITestCondition use10D13assample TestVTI N12 10 D13Item VD 0 1V VS VB 0V VG 0VTO0 8 1 2VMEASUREVTI N VG ID 0 1 A W L W 10 L 0 13 VD 0 1V VS VB 0V VG 0Vto0 8 1 2V 0 96V DetectID VTIshowtheThresholdvoltageinlinearregion VTIRelatedIn LineData 1 Polyin LineAEICD2 VTimplant3 AAin LineAEICD4 GateOXthickness quality5 LDDimplant6 S Dimplant N PPlus 7 Thermalbudget DeviceTestCondition Basic VTI 线性区间 常数电流模式下的开启电压 2 NMOS sIDSATTestCondition use10D13assample TestIDSAT N12 10 D13Item VD VG 1 2V VS VB 0VMEASUREIDSAT N ID W VS VB 0V VG VD 1 2V MeasureID IDSATshowtheSaturationcurrentinworkstatus IDSATRelatedIn LineData 1 Polyin LineAEICD2 VTimplant3 AAin LineAEICD4 GateOXthickness quality5 LDDimplant6 S Dimplant N PPlus 7 Thermalbudget DeviceTestCondition Basic IDSAT 饱和电流 3 NMOS sIOFFTestCondition use10D13assample TestIOFF N12 10 D13Item VD 1 1 1 2V VG VS VB 0VMEASUREIOFF N ID W VG VS VB 0V MeasureID IOFFshowtheleakagecurrentwhendevicewasOFF IOFFRelatedIn LineData 1 S Dimplant N PPlus 2 Wellimplant3 CTETCH4 Co Loop5 AA STIstructure6 SmallDefect7 Thermalbudget VD 1 1 1 2V 1 328V DeviceTestCondition Basic IOFF 器件关闭状况下的漏电流 4 NMOS sBVDSTestCondition use10D13assample TestBVDS N12 10 D13Item VG VS VB 0V VD 0VTO10VMEASUREVBD N VD ID 0 1 A W VG VS VB 0V DetectID BVDSshowtheBrakeDown Soft statusofdevice BVDSRelatedIn LineData 1 GateOXthickness quality2 Charge3 PolyETCH4 Co Loop5 AA STIstructure6 SmallDefect7 Thermalbudget VD 0Vto10V DeviceTestCondition Basic BVDS S D之间的击穿电压 1 NMOS sVTGMTestCondition use10D13assample TestVTGM N12 10 D13Item VD 0 1V VS VB 0V VG 0VTO0 8 1 2VEXTRAPOLATETOVGATMAX SLOPEMEASUREVTGM N VG INTERCEPT 0 5 VD VD 0 1V VS VB 0V VG 0Vto0 8 1 2V 0 96V DetectID VTGMshowtheThresholdvoltageinlinearregion VTGMRelatedIn LineData 1 Polyin LineAEICD2 VTimplant3 AAin LineAEICD4 GateOXthickness quality5 LDDimplant6 S Dimplant N PPlus 7 Thermalbudget DeviceTestCondition Basic VTGM 线性区间 GM模式下的开启电压 红色 Id Vg的斜率蓝色 Id Vg曲线 2 NMOS sVTSATTestCondition use10D13assample TestVTSAT N12 10 D13Item VD 1 2V VS VB 0V VG 0VTO0 8 1 2VMEASUREVTSAT N VG ID 0 1 A W L VD 1 2V VS VB 0V VG 0Vto0 8 1 2V 0 96V DetectID VTSATshowtheThresholdvoltageinsaturationregion VTSATRelatedIn LineData 1 Polyin LineAEICD2 VTimplant3 AAin LineAEICD4 GateOXthickness quality5 LDDimplant6 S Dimplant N PPlus 7 Thermalbudget DeviceTestCondition Basic VTSAT 饱和区间 常数电流模式下的开启电压 3 NMOS sISUBTestCondition use10D13assample TestISUB N12 10 D13Item VD 1 1 1 2V VS VB 0V VG 0 2 1 2VTO1 1 1 2VFINDISUB N MAX VD 1 1 1 2V 1 32V VS VB 0V VG 0 2 1 2Vto1 1 1 2V DetectIB ISUBshowthemax substratecurrent ISUBRelatedIn LineData 1 S Dimplant N PPlus 2 Wellimplant3 CTETCH4 Co Loop5 AA STIstructure6 SmallDefect7 Thermalbudget DeviceTestCondition Basic ISUB 由热电子引起的基底电流 4 NMOS sDIBLTestCondition use10D18assample TestDIBL N12 10 D13Item DIBL N VTLIN VTSAT 1 2 0 05 DIBLshowthedraininducedbarrierloweringlevelDIBLRelatedIn LineData 1 Polyin LineAEICD2 VTimplant3 AAin LineAEICD4 GateOXthickness quality5 LDDimplant6 S Dimplant N PPlus 7 Thermalbudget DeviceTestCondition Basic DIBL 由漏电流VD引起的迁移效应的水准 5 NMOS sGAMMATestCondition use10D13assample TestGAMMA N12 10 D13Item a VD 0 1V VS 0V VB 0V VG 0VTO0 8 1 2V EXTRAPOLATETOVGATMAX SLOPE MEASUREVTGM 0 VG INTERCEPT 0 5 VD b VD 0 1V VS 0V VB 0 5 1 2V VG 0VTO0 8 1 2V EXTRAPOLATETOVGATMAX SLOPE MEASUREVTGM VB VG INTERCEPT 0 5 VD C GAMMA N12 VTGM VB VTGM 0 Phis 0 5 1 2 1 2 Phis 1 2 Phis 0 887488 VD 0 1V VS 0V VG 0to1 1 1 2V DetectID GAMMAshowthemax substratecurrent GAMMARelatedIn LineData 1 Polyin LineAEICD2 VTimplant3 AAin