单片机-温度控制系统-外文翻译-外文文献-英文文献-中英翻译

1 Design of the Temperature Control System Based on AT89C51 ABSTRACT The principle and functions of the temperature control system based on micro controller AT89C51 are studied and the temperature measurement unit consists of the 1 Wire bus digital temperature sensor DS18B20 The system can be expected to detect the preset temperature display time and save monitoring data An alarm will be given by system if the temperature exceeds the upper and lower limit value of the temperature which can be set discretionarily and then automatic control is achieved thus the temperature is achieved monitoring intelligently within a certain range Basing on principle of the system it is easy to make a variety of other non linear control systems so long as the software design is reasonably changed The system has been proved to be accurate reliable and satisfied through field practice KEYWORDS AT89C51 micro controller DS18B20 temperature 1 INTRODUCTION Temperature is a very important parameter in human life In the modern society temperature control TC is not only used in industrial production but also widely used in other fields With the improvement of the life quality we can find the TC appliance in hotels factories and home as well And the trend that TC will better serve the whole society so it is of great significance to measure and control the temperature Based on the AT89C51 and temperature sensor DS18B20 this system controls the condition temperature intelligently The temperature can be set discretionarily within a certain range The system can show the time on LCD and save monitoring data and automatically control the temperature when the condition temperature exceeds the upper and lower limit value By doing so it is to keep the temperature unchanged The system is of high anti jamming high control precision and flexible design it also fits the rugged environment It is mainly used in people s life to improve the quality of the work and life It is also versatile so that it can be convenient to extend the use of the system So the design is of profound importance The general design hardware design and software design of the system are covered 1 1 Introduction The 8 bit AT89C51 CHMOS microcontrollers are designed to handle high speed calculations and fast input output operations MCS 51 microcontrollers are typically 2 used for high speed event control systems Commercial applications include modems motor control systems printers photocopiers air conditioner control systems disk drives and medical instruments The automotive industry use MCS 51 microcontrollers in engine control systems airbags suspension systems and antilock braking systems ABS The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on chip peripheral functions set such as automotive power train control vehicle dynamic suspension antilock braking and stability control applications Because of these critical applications the market requires a reliable cost effective controller with a low interrupt latency response ability to service the high number of time and event driven integrated peripherals needed in real time applications and a CPU with above average processing power in a single package The financial and legal risk of having devices that operate unpredictably is very high Once in the market particularly in mission critical applications such as an autopilot or anti lock braking system mistakes are financially prohibitive Redesign costs can run as high as a 500K much more if the fix means 2 back annotating it across a product family that share the same core and or peripheral design flaw In addition field replacements of components is extremely expensive as the devices are typically sealed in modules with a total value several times that of the component To mitigate these problems it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions This complete and thorough validation necessitates not only a well defined process but also a proper environment and tools to facilitate and execute the mission successfully Intel Chandler Platform Engineering group provides post silicon system validation SV of various micro controllers and processors The system validation process can be broken into three major parts The type of the device and its application requirements determine which types of testing are performed on the device 1 2 The AT89C51 provides the following standard features 4Kbytes of Flash 128 bytes of RAM 32 I O lines two 16 bittimer counters a five vector two level interrupt architecture a full duple ser ial port on chip oscillator and clock circuitry In addition the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes The Idle Mode stops the CPU while allowing the RAM timer counters serial port and interrupt sys tem to continue functioning The Power down Mode saves the 3 RAM contents but freezes the oscil lator disabling all other chip functions until the next hardware reset 1 3Pin Description VCC Supply voltage GND Ground Port 0 Port 0 is an 8 bit open drain bi directional I O port As an output port each pin can sink eight TTL inputs When 1s are written to port 0 pins the pins can be used as high impedance inputs Port 0 may also be configured to be the multiplexed low order address data bus during accesses to external program and data memory In this mode P0 has internal pull ups Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification External pull ups are required during program verification Port 1 Port 1 is an 8 bit bi directional I O port with internal pull ups The Port 1 output buffers can sink so urce four TTL inputs When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs As inputs Port 1 pins that are externally being pulled low will source current IIL because of the internal pullups Port 1 also receives the low order address bytes during Flash programming and verification Port 2 Port 2 is an 8 bit bi directional I O port with internal pull ups The Port 2 output buffers can sink source four TTL inputs When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current IIL because of the internal pull ups Port 2 emits the high order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current IIL because of the internal pull ups Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pull ups when emitting 1s During accesses to external data memory that use 8 bit addresses MOVX RI Port 2 emits the contents of the P2 Special Function Register Port 2 also receives the high order address bits and some control signals durin Flash programming and verification Port 3 Port 3 is an 8 bit bi directional I O port with internal pull ups The Port 3 output buffers can sink sou rce four TTL inputs When 1s are written to Port 3 pins they are pulled high by the internal pull ups and can be used as inputs As inputs Port 4 3 pins that are externally being pulled low will source current IIL because of the pull ups Port 3 also serves the functions of various special features of the AT89C51 as listed below RST Reset input A high on this pin for two machine cycles while the oscillator is running resets the device ALE PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory This pin is also the program pulse input PROG during Flash programming In normal operation ALE is emitted at a constant rate of 1 6 the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped duri ng each access to external Data Memory If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With the bit set ALE is active only during a MOVX or MOVC instruction Otherwise the pin is weakly pulled high Setting the ALE disable bit has no effect if the microcontroller is in external execution mode PSEN Program Store Enable is the read strobe to external program memory When theAT89C51 is executing code from external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory EA VPP External Access Enable EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note however that if lock bit 1 is programmed EA will be internally latched on reset EA should be strapped to VCC for internal program executions This pin alsreceives the 12 volt programming enable voltage VPP during Flash programming for parts that require 12 volt VPP XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit XTAL2 Output from the inverting oscillator amplifier Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output respectively of an inverting amplifier which can be configured for use as an on chip oscillator as shown in Figure 1 Either a quartz crystal or ceramic resonator may be used To drive the device from an external clock source XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a 5 divide by two flip flop but minimum and maximum voltage high and low time specifications must be observed Idle Mode In idle mode the CPU puts itself to sleep while all the on chip peripherals remain active The mode is invoked by software The content of the on chip RAM and all the special functions registers remain unchanged during this mode The idle mode can be terminated by any enabled interrupt or by a hardware reset It should be noted that when idle is terminated by a hard ware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control On chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory Power down Mode In the power down mode the oscillator is stopped and the instruction that invokes power down is the last instruction executed The on chip RAM and Special Function Registers retain their values until the power down mode is terminated The only exit from power down is a hardware reset Reset redefines the SFRS but does not change the on chip RAM The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize The AT89C51 code memory array is programmed byte by byte in either programming mode To program any nonblank byte in the on chip Flash Memory the entire memory must be erased using the Chip Erase Mode 2 Programming Algorithm Before programming the AT89C51 the address data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4 To program the AT89C51 take the following steps 1 Input the desired memory location on the address lines 2 Input the appropriate data byte on the data lines 3 Activate the correct combination of control signals 4 Raise EA VPP to 12V for the high voltage programming mode 5 Pulse ALE PROG once to program a byte in the Flash array or the lock bits The byte write cycle is self timed and typically takes no more than 1 5 ms Repeat steps 1 through 5 changing the address and data for the entire array or until the end of the object file is reached Data Polling The AT89C51 features Data Polling to indicate the end of a write cycle During a write cycle an attempted read of the last byte written will result in the complement of the written 6 datum on PO 7 Once the write cycle has been completed true data are valid on all outputs and the next cycle may begin Data Polling may begin any time after a write cycle has been initiated 2 1Ready Busy The progress of byte programming can also be monitored by the RDY BSY output signal P3 4 is pulled low after ALE goes high during programming to indicate BUSY P3 4 is pulled high again when programming is done to indicate READY Program Verify If lock bits LB1 and LB2 have not been programmed the programmed code data can be read back via the address and data lines for verification The lock bits cannot be verified directly Verification of the lock bits is achieved by observing that their features are enabled 2 2 Chip Erase The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE PROG low for 10 ms The code array is written with all 1 s The chip erase operation must be executed before the code memory can be re programmed 2 3 Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H 031H and 032H except that P3 6 and P3 7 must be pulled to a logic low The values returned areas follows 030H 1EH indicates manufactured by Atmel 031H 51H indicates 89C51 032H FFH indicates 12V programming 032H 05H indicates 5V programming 2 4 Programming Interface Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals The write operation cycle is self timed and once initiated will automatically time itself to completion A microcomputer interface converts information between two forms Outside the microcomputer the information handled by an electronic system exists as a physical signal but within the program it is represented numerically The function of any 7 interface can be broken down into a number of operations which modify the data in some way so that the process of conversion between the external and internal forms is carried out in a number of steps An analog to digital converter ADC is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values If the output of the transducer does not vary continuously no ADC is necessary In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface the input output section of the microcomputer itself Output interfaces take a similar form the obvious difference being that here the flow of information is in the opposite direction it is passed from the program to the outside world In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for digital to analog converter DAC This subroutine passes information in turn to an output device which produces a corresponding electrical signal which could be converted into analog form using a DAC Finally the signal is conditioned usually amplified to a form suitable for operating an actuator The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world and some kind of interface must be used to translate them to a more appropriate form The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers We have seen that in microcomputers information is represented as discrete patterns of bits this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off where each bit might represent the state of a switch or actuator To solve real world problems a microcontroller must have more than just a CPU a program and a data memory In addition it must contain hardware allowing the CPU to access information from the outside world Once the CPU gathers information and processes the data it must also be able to effect change on some portion of the outside world These hardware devices called peripherals are the CPU s window to the outside The most basic form of peripheral available on microcontrollers is the general purpose I70 port Each of the I O pins can be used as either an input or an output The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program Each output pin may be driven to either a logic one or a logic zero by using CPU 8 instructions to pin may be viewed or read by the CPU using program instructions Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit serially with external devices Using a bit serial format instead of bit parallel format requires fewer I O pins to perform the communication function which makes it less expensive but slower Serial transmissions are performed either synchronously or asynchronously 3 SYSTEM GENERAL DESIGN The hardware block diagram of the TC is shown in Fig 1 The system hardware includes the micro controller temperature detection circuit keyboard control circuit clock circuit Display alarm drive circuit and external RAM Based on the AT89C51 the DS18B20 will transfer the temperature signal detected to digital signal And the signal is sent to the micro controller for processing At last the temperature value is showed on the LCD 12232F Thes