湘潭大学本部2011级EDA作业答案 (2).docx

答案由个人做出，可能有不全或错误之处，欢迎大家批评指正。2.3什么是重载函数？重载算符有何用处？如何调用重载算符函数？同样名称的函数可以用不同的数据类型作为此函数的参数定义多次，以此定义的函数称为重载函数。被重载的运算符能够对新的数据类型进行操作，或者允许不同的数据类型之间用此运算符进行运算。按重载运算符的方式严格调用重载算符函数2.15图2.18中的f_adder是一位全加器，cin是输入进位，cout是输出进位，试给输出的电路的VHDL描述。library ieee;use ieee.std_logic_1164.all; entity ff is port (x,y,clock:in std_logic; sum:out std_logic); end; architecture one of ff is component f_adder port(a,b,ci:in std_logic; su,co:out std_logic); end component; component df port(d,cl:in std_logic; q1:out std_logic); end component; signal cout,tmp:std_logic; begin u1:f_adder port map(a=x,b=y,ci=tmp,su=sum,co=cout); u2:df port map(d=cout,cl=clock,q1=tmp); end architecture one;library ieee;use ieee.std_logic_1164.all; entity df is port (d,cl:in std_logic; q1:out std_logic); end; architecture two of df is signal qq:std_logic; begin process(cl,qq) begin if cl event and cl=1 then qq=d; end if; end process; q1a,b1=b,cou=d,so=e); u2:h_adder port map(a1=e,b1=ci,cou=f,so=su); u3:or2a port map(a1=d,b1=f,c=co); end architecture three;library ieee;use ieee.std_logic_1164.all; entity h_adder is port (a1,b1:in std_logic; so,cou:out std_logic); end; architecture four of h_adder is begin so=not(a1 xor(not b1); cou=a1 and b1; end architecture four;library ieee;use ieee.std_logic_1164.all; entity or2a is port (a1,b1:in std_logic; c:out std_logic); end; architecture five of or2a is begin c0); elsif clk event and clk=1 then if en=1 then if cqi0); end if; end if; end if; if cqi=99 then cout=1; else cout=0; end if; cq=cqi; end process;end behav;2.2子程序调用与元件例化有何区别？函数与过程在具体使用上有何不同？子程序调用与元件例化没有本质的区别，调用一个子程序在硬件上相当于放置了一个电路模块。函数和过程的不同在于：函数只有一个输出，只能通过函数体内的RETURN语句来实现，函数体内不能有信号赋值语句；而过程却可以有不止一个输出，而且是通过过程体内的信号赋值语句或者变量赋值语句来实现的，过程体内的RETURN语句没有用处，因此不少过程都将其省略了。函数的调用只能通过表达式来实现，过程的调用则是通过过程调用语句来实现的。2.12判断下面3例VHDL程序中是否有错误，如有错误指出原因。程序1：把if EN=1改为if EN=1;把B=A改为B:=A程序2：variable a,b,c:integer错误，变量的定义和使用只能在进程和子程序中使用。 c=a+b错误，变量的赋值用“:=”程序3：c:out std_logic;这个分号不能有end sam2改为end mux21(实体名要一致)；c:=a和c:=b改为c=a和c=b（a,b,c都是信号，信号的赋值用“ cout cout cout cout cout cout cout cout NULL; end case; end process;end;IF：library ieee;use ieee.std_logic_1164.all;entity sss is port (a: in std_logic_vector(2 downto 0); cout:out std_logic_vector(7 downto 0);end ;architecture one of sss isbegin process(a) begin if a=000 then cout =11111110; elsif a=001 then cout =11111101; elsif a=010 then cout =11111011; elsif a=011 then cout =11110111; elsif a=100 then cout =11101111; elsif a=101 then cout =11011111; elsif a=110 then cout =10111111; elsif a=111 then cout =01111111; end if; end process;end;16设计5位可变模数计数器。设计要求：令输入信号M1和M0控制计数模，即令（M1，M0）=(0，0)时为模19加法计数器，（M1，M0）=(0，1)时为模4计数器，（M1，M0）=(1，0)时为模10加法计数器，（M1，M0）=(1，1) 时为模6计数器。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mod_cal is port ( M1, M0: in bit; count: out std_logic_vector(4 downto 0); clk: in std_logic); end entity; architecture behav of mod_cal is signal count1:std_logic_vector(4 downto 0); begin process(clk, M1,M0) variable sel: bit_vector(1 downto 0); begin sel:=M1&M0; if clk event and clk=1 then count1 if count1=10011 then count1 if count1=00100 then count1 if count1=01010 then count1 if count1=00110 then count1=00000;end if; end case; end if; end process; count=count1; end behav;24用VHDL设计一个实现三输入的多数表决器library ieee;use ieee.std_logic_1164.all;entity bjq3 is port(a,b,c:in std_logic; y:out std_logic);end;architecture x of bjq3 is signal ty:std_logic_vector(2 downto 0);begin ty=a&b&c; with ty select y=0 when 000, 0 when 001, 0 when 010, 1 when 011, 0 when 100, 1 when 101, 1 when 110, 1 when 111, X when others;end;26用并行信号赋值语句设计8选1数据选择器library ieee;use ieee.std_logic_1164.all;entity sss is port (a,b,c,d,e,f,g,h,i:in std_logic; s:in std_logic_vector(2 downto 0); y:out std_logic);end ;architecture one of sss is begin y=a when s=000 else b when s=001 else c when s=010 else d when s=011 else e when s=100 else f when s=101 else g when s=110 else h when s=111 else X;end;31将以下程序段转换为WHEN_ELSE语句： process(a,b,c,d) begin if a=0 AND b=1 then next1=1101; elsif a=0 then next1=d; elsif b=1 then next1=c; else next1=1011; end if; end process;语句为：next1=1101 when a=0 and b=1 else d when a=0 else c when b=1 else 1011;34哪些情况下需要用到程序包STD_LOGIC_UNSIGNED?试举一例。VHDL描述中若有不同类型数据相加、相减时需要用到程序包STD_LOGIC_UNSIGNED中的“+”、“-”算符重载函数。如：SIGNAL Q1 ：STD_LOGIC_VECTOR (3 DOWNTO 0 ); BEGIN PROCESS ( CLK ) BEGIN IF CLK EVENT AND CLK=1THEN Q1x,y=y,diff=d,s_out=e); u2:h_subber PORT MAP(x=d,y=sub_in,diff=diffr,s_out=f); u3:or2a PORT MAP(a=f,b=e,c=sub_out);END ARCHITECTURE ONE;-底层文件1：或门LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY or2a IS PORT(a,b:IN STD_LOGIC;c:OUT STD_LOGIC);END ENTITY or2a;ARCHITECTURE one OF or2a IS BEGIN c = a OR b;END ARCHITECTURE one;-底层文件2：半减器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY h_subber IS PORT(x,y:IN STD_LOGIC; diff,s_out:OUT STD_LOGIC);END ENTITY h_subber;ARCHITECTURE ONE OF h_subber IS SIGNAL xyz: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN xyz diff=0;s_out diff=1;s_out diff=1;s_out diff=0;s_out NULL; END CASE; END PROCESS;END ARCHITECTURE ONE;(2)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY f_subber IS PORT(x,y,sub_in:IN STD_LOGIC; diffr,sub_out:OUT STD_LOGIC);END;ARCHITECTURE ONE OF f_subber IS BEGIN diffr=(x nor y)nor sub_in; sub_out=(not x)and y)or(sub_in and(not(x nor y);END ARCHITECTURE ONE;(3) -顶层文件：8位全减器Library ieee; use ieee.std_logic_1164.all;Entity f_subber8 is Port(a,b:in std_logic_vector(7 downto 0); sin:in std_logic; sout:out std_logic; c:out std_logic_vector(7 downto 0);End; Architecture behav of f_subber8 is Component f_subber Port(x,y,sub_in:in std_logic; diffr,sub_out:out std_logic); End component; Signal stmp:std_logic_vector(8 downto 0); Begin stmp(0)=sin; soutstmp(i),x=a(i),y=b(i),diffr=c(i),sub_out=stmp(i+1); End generate; End;-底层文件1：或门LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY or2a IS PORT(a,b:IN STD_LOGIC;c:OUT STD_LOGIC);END ENTITY or2a;ARCHITECTURE one OF or2a IS BEGIN c = a OR b;END ARCHITECTURE one;-底层文件2：半减器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY h_subber IS PORT(x,y:IN STD_LOGIC; diff,s_out:OUT STD_LOGIC);END ENTITY h_subber;ARCHITECTURE ONE OF h_subber IS SIGNAL xyz: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN xyz diff=0;s_out diff=1;s_out diff=1;s_out diff=0;s_out NULL; END CASE; END PROCESS;END ARCHITECTURE ONE;-底层文件：全减器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY f_subber IS PORT(x,y,sub_in:IN STD_LOGIC; diffr,sub_out:OUT STD_LOGIC);END;ARCHITECTURE ONE OF f_subber IS COMPONENT h_subber PORT(x,y:IN STD_LOGIC; diff,S_out:OUT STD_LOGIC); END COMPONENT; COMPONENT or2a PORT(a,b:IN STD_LOGIC; c:OUT STD_LOGIC); END COMPONENT; SIGNAL d,e,f: STD_LOGIC; BEGIN u1:h_subber PORT MAP(x=x,y=y,diff=d,s_out=e); u2:h_subber PORT MAP(x=d,y=sub_in,diff=diffr,s_out=f); u3:or2a PORT MAP(a=f,b=e,c=sub_out);END ARCHITECTURE ONE;37图2.20有3张由D触发器构成的电路图，请分别给出它们的VHDL描述。-底层文件1：2选1选择器library ieee;use ieee.std_logic_1164.all;entity mux21a is port (a,b,s:in bit; z:out bit);end entity mux21a;architecture one of mux21a is begin z=a when s=0 else b;end architecture one; -底层文件2：D触发器library ieee;use