数字下变频论文面向DDC应用的嵌入式SoC设计.doc

数字下变频论文：面向DDC应用的嵌入式SoC设计【中文摘要】当前软件无线电技术在无线通信系统中广泛的应用,使的无线通信设备能够应用到人们的生活中。软件无线电的核心思想是使模数转换器尽量接近射频前端,输出中频数字信号,这样后续的变频滤波、调制和解调、通信协议处理等都采用数字电路和软件来处理。数字下变频电路(Digital Down Conversion,DDC)是软件无线电的核心技术之一,它将模数转换器采样的中频数字信号变频滤波到低频数字信号,适于后续的DSP或微处理器完成基带信号处理。论文针对数字下变频的应用设计实现一个嵌入式SoC。SoC采用基于平台的设计方法,系统中的各个功能模块移植复用已有的IP核,加快系统设计的速度,提高设计的效率。SoC的核心采用开源的OpenRISC处理器,SoC通过Wishbone总线连接各个IP模块、存储设备和IO外设。SoC采用专用的DMA通道对DDC的连续输出数据进行采样和存储,减少总线操作,提高系统性能。OpenRISC处理器执行软件算法对DDC输出的基带信号数据进行处理。对设计的SoC系统平台进行RTL动态仿真,验证系统中各个模块的功能、模块之间的数据传输和协同工作。本文采用软硬件协同验证的方法,通过由C语言编写的高级程序编译生成CPU执行的二进制代码,生成测试激励,验证系统的功能。此外,由于FPGA拥有很好的灵活性和仿真速度,采用FPGA实现系统的硬件原型平台,运行软件程序,以快速验证SoC的功能。在完成SoC的RTL动态仿真后,使用Xilinx公司的ML510 FPGA开发板对系统进行了FPGA原型验证。SoC的前端设计和验证完成后,采用EDA工具进行了系统的逻辑综合、时序分析、形式验证、布局布线、物理验证和后仿真等步骤,最后得到用于生产的SoC版图文件。SoC采用捷智半导体公司的0.18m SiGe BiCMOS工艺库实现,在最坏工作条件下,芯片运行速度达到100MHz,面积为3.33.3mm2,功耗为154.3mW。【英文摘要】Software radio technology is now widely used in wireless communication systems, and more wireless communication devices are used in peoples lives. The idea of software radio is to make the analog digital converter as close to the RF front end, then output digital signal, so that subsequent frequency filtering, modem, communications protocol processing, can be processed by digital circuit and software. Digital down conversion circuit is one of the core technology of software radio, it will sample IF digital signal to the low-frequency digital signal. DSP or microprocessor can process the baseband signal.In this paper, we design and implementation of an embedded SoC for the application of DDC. SoC design methodology is based on platform; each module in the system is transferred from the existing IP core. By this way we can speed up the system design, and improve the success rate of design. The SoC use open source OpenRISC processor, and use wishbone bus connect IP modules, storage devices and IO peripherals. SoC use a dedicated DMA channel sample the continuous DDC output data and storage, reducing bus operation, improving system performance. OpenRISC processor executes the software algorithms processing DDC output baseband signal.When completing the design of SoC platform, do the system RTL simulation, validating the system function, the data transmission between modules and cooperation. In this paper, we use hardware and software co-verification way to verify system functionality. Write C language programs, compiled to binary code executed by the CPU to generate test stimulus. FPGA has good flexibility and speed. In this paper, we use FPGA to implement the system hardware prototyping platform, running a large number of software programs to verify the function of SoC. After the completion of RTL simulation, then use Xilinxs ML510 FPGA development board implement a system prototype for verification.When finishing the front-end SoC design and verification, use EDA tools to do logic synthesis, timing analysis, formal verification, P&R, physical verification, post-layout simulation etc. At last we generate SoC layout file. The SoC use Jazz Semiconductors 0.18m SiGe BiCMOS technology library to implement and the chip is running at 100MHz, area is 3.33.3mm2, power consumption is 154.3mW.【关键词】数字下变频 嵌入式系统 FPGA EDA工具【英文关键词】Digital down conversion Embedded System FPGA EDA tools【目录】面向DDC应用的嵌入式SoC设计摘要4-5ABSTRACT5第1章 绪论8-131.1 课题背景及研究意义8-91.2 国内外研究现状9-111.2.1 数字下变频的实现技术9-101.2.2 SoC 设计技术101.2.3 可编程逻辑器件10-111.3 论文主要研究工作111.4 论文结构11-13第2章 数字下变频的工作原理13-172.1 数字下变频的电路结构132.2 数字下变频的关键技术13-162.2.1 数字信号处理链路13-142.2.2 DDS 功能模块的设计14-152.2.3 累加器模块电路设计152.2.4 混频器设计15-162.2.5 滤波器组数字电路设计162.3 本章小结16-17第3章 嵌入式SOC 的结构与实现17-313.1 系统结构的设计17-193.2 主要功能模块介绍19-253.2.1 OR1200 CPU19-203.2.2 Wishbone Conmax20-223.2.3 Memory Controller22-233.2.4 UART233.2.5 DMA23-243.2.6 DDC 和WB_DDC_CFG24-253.3 SOC 的RTL 仿真25-303.3.1 编译工具链25-263.3.2 测试平台的搭建26-273.3.3 系统平台的RTL 验证27-303.4 本章小结30-31第4章 嵌入式SOC 的FPGA 原型验证31-414.1 FPGA 设计流程31-324.2 SOC 的FPGA 实现32-344.2.1 数据文件准备32-334.2.2 设计的实现约束334.2.3 FPGA 实现结果33-344.3 基于FPGA 的原型验证34-404.3.1 FPGA 板级验证平台35-364.3