用VHDL编写的各种功能的计数器代码.doc

Library IEEE ;use IEEE.std_logic_1164.all ;use IEEE.std_logic_arith.all ;ENTITY counters ISPORT(d: IN INTEGER RANGE 0 TO 255;clk: INBIT;clear: INBIT;ld: INBIT;enable: INBIT;up_down: INBIT;qa: OUT INTEGER RANGE 0 TO 255;qb: OUT INTEGER RANGE 0 TO 255;qc: OUT INTEGER RANGE 0 TO 255;qd: OUT INTEGER RANGE 0 TO 255;qe: OUT INTEGER RANGE 0 TO 255;qf: OUT INTEGER RANGE 0 TO 255;qg: OUT INTEGER RANGE 0 TO 255;qh: OUT INTEGER RANGE 0 TO 255;qi: OUT INTEGER RANGE 0 TO 255;qj: OUT INTEGER RANGE 0 TO 255;qk: OUT INTEGER RANGE 0 TO 255;ql: OUT INTEGER RANGE 0 TO 255;qm: OUT INTEGER RANGE 0 TO 255;qn: OUT INTEGER RANGE 0 TO 255);END counters;ARCHITECTURE a OF counters ISBEGIN- An enable counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;BEGINIF (clkEVENT AND clk = 1) THENIF enable = 1 THENcnt := cnt + 1;END IF;END IF;qa= cnt;END PROCESS;- A synchronous load counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;BEGINIF (clkEVENT AND clk = 1) THENIF ld = 0 THENcnt := d;ELSEcnt := cnt + 1;END IF;END IF;qb=cnt;END PROCESS;- A synchronous clear counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;BEGINIF (clkEVENT AND clk = 1) THENIF clear = 0 THENcnt := 0;ELSEcnt := cnt + 1;END IF;END IF;qc=cnt;END PROCESS;- An up/down counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;VARIABLEdirection : INTEGER;BEGINIF (up_down = 1) THENdirection := 1;ELSEdirection := -1;END IF;IF (clkEVENT AND clk = 1) THENcnt := cnt + direction;END IF;qd=cnt;END PROCESS;- A synchronous load enable counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;BEGINIF (clkEVENT AND clk = 1) THENIF ld = 0 THENcnt := d;ELSEIF enable = 1 THENcnt := cnt + 1;END IF;END IF;END IF;qe=cnt;END PROCESS;- An enable up/down counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;VARIABLEdirection : INTEGER;BEGINIF (up_down = 1) THENdirection := 1;ELSEdirection := -1;END IF;IF (clkEVENT AND clk = 1) THENIF enable = 1 THENcnt := cnt + direction;END IF;END IF;qf=cnt;END PROCESS;- A synchronous clear enable counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;BEGINIF (clkEVENT AND clk = 1) THENIF clear = 0 THENcnt := 0;ELSEIF enable = 1 THENcnt := cnt + 1;END IF;END IF;END IF;qg=cnt;END PROCESS;- A synchronous load clear counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;BEGINIF (clkEVENT AND clk = 1) THENIF clear = 0 THENcnt := 0;ELSEIF ld = 0 THENcnt := d;ELSEcnt := cnt + 1;END IF;END IF;END IF;qh=cnt;END PROCESS;- A synchronous load up/down counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;VARIABLEdirection : INTEGER;BEGINIF (up_down = 1) THENdirection := 1;ELSEdirection := -1;END IF;IF (clkEVENT AND clk = 1) THENIF ld = 0 THENcnt := d;ELSEcnt := cnt + direction;END IF;END IF;qi=cnt;END PROCESS;- A synchronous load enable up/down counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;VARIABLEdirection : INTEGER;BEGINIF (up_down = 1) THENdirection := 1;ELSEdirection := -1;END IF;IF (clkEVENT AND clk = 1) THENIF ld = 0 THENcnt := d;ELSEIF enable = 1 THENcnt := cnt + direction;END IF;END IF;END IF;qj=cnt;END PROCESS;- A synchronous clear load enable counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;BEGINIF (clkEVENT AND clk = 1) THENIF clear = 0 THENcnt := 0;ELSEIF ld = 0 THENcnt := d;ELSEIF enable = 1 THENcnt := cnt + 1;END IF;END IF;END IF;END IF;qk=cnt;END PROCESS;- A synchronous clear up/down counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;VARIABLEdirection : INTEGER;BEGINIF (up_down = 1) THENdirection := 1;ELSEdirection := -1;END IF;IF (clkEVENT AND clk = 1) THENIF clear = 0 THENcnt := 0;ELSEcnt := cnt + direction;END IF;END IF;ql=cnt;END PROCESS;- A synchronous clear enable up/down counterPROCESS (clk)VARIABLEcnt: INTEGER RANGE 0 TO 255;VARIABLEdirection : INTEGER;BEGINIF (up_down = 1) THENdirection := 1;ELSEdirection := -1;END IF;IF (clkEVENT AND clk = 1) THENIF clear = 0 THENcnt := 0;ELSEIF enable = 1 THENcnt := cnt + direction;END IF;END IF;END IF;qm=cnt;END PROCESS;- A modulus 200 up count