modelsim仿真测试 实验三.doc

实验3.1. modelsim仿真测试一、实验目的1、分析分频器的VHDL代码，了解信号和变量的差别。2、学习modelsim软件环境下，采用测试向量进行测试的方法。包括：激励文件的建立和测试实现。二、实验步骤1.1. modelsim的批处理操作流程建立一个工程File-New Project Wizard, 信号描述library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity div_Signal isgeneric (div_nx2:positive:=4);port (clk: in std_logic;q: out std_logic);end div_Signal;architecture behav of div_Signal isSIGNAL fre_N : integer range 0 to div_nx2:=0;SIGNAL clk_tmp: std_logic:=0;BEGINq = div_nx2 - 1 then fre_N = 0; clk_tmp = not clk_tmp;else fre_N =div_nx2-1 then fre_N := 0; Clk_Out = not Clk_Out; else fre_N:=fre_N+1;end if; end if;end process;clkout = Clk_Out;end Behavioral;方法1： 方法2：存为：div_signal_do.dovsim work.div_signal add wave sim:/div_signal/*force -freeze sim:/div_signal/clk 1 0, 0 10 ns -r 20run 400ns在编译后，获得了逻辑网表，但未开始仿真。可以直接运行DO文件。点击Next，我们将其工程存储在D:Tempex1下（注意：存储路径中一定不能有空格或中文，否则找不到相关文件），工程命名为ex1，如下所示 1.2. 使用测试向量testbench新建项目，添加新文件：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cntx isport(clk,rst,en: in std_logic; q: out std_logic_vector(3 downto 0);end cntx;architecture behave of cntx is signal q_n: std_logic_vector(3 downto 0);begin process(clk, rst, en, q_n) begin if (rst = 1) then q_n 0); elsif rising_edge(clk) then if en = 1 then q_n = q_n + 1; end if; end if; end process; q q ,clk=clk, en=en ,rst= rst); simProcess: process begin rst = 1; wait for 50 ns; rst = 0 ; wait for 1000 ns; rst = 0 ; end process simprocess; en = 0 after 0 ns, 1 after 50 ns, 0 after 850 ns, 1 after 900 ns; ClockProcess: process(clk, rst) begin if (rst = 1) then clk = 0; else clk New Project Wizard,点击Next，设置如下所示然后，点击Next，如下所示这一页不需要修改，点击Next，如下图所示，Family：CYCLONE IV E,芯片选择：EP4CE15F17C8，这里面有个地方需要说明一下EP4CE15F17C8N,N是代表无铅，跟芯片型号没关系；而EP4CE15F17C8L癿L是低电压的意思，就是说这个是低电压版本。这个地方大家要注意下，我们使用的是正常的版本，即型号为EP4CE15F17C8。如下图红圈处。然后点击Next，Next，Finish，完成工程建立。点击tool/sopc builder: package require :quartus:projectset_location_assignment PIN_M1 -to resetset_location_assignment PIN_R9 -to clk50mset_location_assignment PIN_J1 -to led0set_location_assignmentPIN_J2-to led1set_location_assignmentPIN_K1-to led2set_location_assignmentPIN_K2-to led3重新编译系统，下载硬件到FPGA实验板。然后打开软件开发环境：第一次运行，可能会要求设置工作目录，可改为项目路径，如：d:codework打开typedef signed char alt_8;typedef unsigned char alt_u8;typedef signed short alt_16;typedef unsigned short alt_u16;typedef signed long alt_32;typedef unsigned long alt_u32;typedef long long alt_64;typedef unsigned long long alt_u64;#include system.h#include #include altera_avalon_pio_regs.hvoid delay(void) unsigned int i; i=100000; while(i0) i-; int alt_main(void) unsigned char led_data; unsigned int led_code; while(1) for(led_data=0;led_data4;led_data+) led_code=0x01led_data; IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE,led_code); delay(); return 0;#include system.h#include #include altera_avalon_pio_regs.hint main() alt_u8 led_data=0x2; alt_u8 dir=0; v