数字逻辑与部件设计实验报告 - Google Code.doc

数字逻辑与部件设计实验报告 07300700042 张璞数字逻辑与部件设计实验报告学号：07300700042姓名：张璞实验一 译码器和编码器3实验二 七段显示译码器的设计.10实验三 加法器、算术逻辑单元及快速进位电路的设计13实验四 触发器和寄存器.19实验五 计数器的设计.24实验六 有限状态机31实验七 总线传输实验.43实验一 译码器和编码器实验要求1 用与非门设计一个3-8译码器74LS138，除了下述真值表中的输入输出信号外，增加三个控制信号G1、G2A、G2B，当G1位高电平，G2A和G2B同时为低电平时，实现如表中的正常译码，否则Y0-Y7都为高电平。输入输出S2S1S0Y0Y1Y2Y3Y4Y5Y6Y700001111111001101111110101101111101111101111100111101111011111101111011111101111111111102 设计一个如下表逻辑功能的8-3普通编码器。输入输出I0I1I2I3I4I5I6I7F0F1F210000000000010000000010010000001000010000011000010001000000010010100000010110000000011113 设计一个8-3优先编码器实验目的1、 熟悉实验仪的使用方法，熟悉基本的VHDL语言的语法规范，熟悉卡诺图的化简方法，熟悉德摩根定律。2、 熟悉VHDL中if语句的使用，特别注意if语句优先级的问题。实验过程及讨论1、 在第一个实验中，输入输出地真值表都已经给出，所以首先对每个输出做化简工作。这些函数都是三变量的，所以化简相对容易，经过化简可以得到如下布尔函数：由于本实验要求是用与非门来实现，而上面的都是用非门和或门来实现的，所以运用德摩根定律，可以将上述的布尔函数等价转化为如下的布尔函数：对上述的布尔函数用与非门来实现就非常容易了。另外，本实验的要求中还要求有三个控制信号G1、G2A、G2B，当G1位高电平，G2A和G2B同时为低电平时，实现如表中的正常译码，否则Y0-Y7都为高电平。所以可以增加一个信号check，表示三个控制信号是否满足要求，check的布尔函数如下：，把这个控制信号与每个输出用与非门连接起来就能得到满足所有要求的输出函数。设计完毕。2、 第二个实验由于输入是8变量的，所以无法用卡诺图手工化简，如果不使用if语句，需要用基本的与门、非门和或门把这些变量连接起来，实现真值表中所示的函数的功能。每个输出对应的布尔函数为：设计完毕。3、 由于要实现8-3优先编码器，VHDL语言中的if语句正好可以用在这里，if语句必须在process中使用，而在一个process中，所有语句都是顺序执行的，if的判断是顺序的，所以判断和执行的先后顺序就代表了优先级。在我的设计中I7的优先级最高，I0的优先级最低，所以在用if语句判断的时候是从I7是否为1开始，逐个递减直到I0结束。另外，在实验3中，需要注意的是，在引脚锁定的时候，由于I0的优先级是最低的，所以需要把I0的引脚注释掉，否则编译的时候会报错。由于是第一次实验，所以忘记把Number of Clock Buffers的值设置为0，造成编译的时候报错，后经询问老师才得以解决。实验代码与引脚锁定1、3-8译码器实验代码library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity decoder_3_8 is Port ( S2 : in std_logic; S1 : in std_logic; S0 : in std_logic; G1 : in std_logic; G2A : in std_logic; G2B : in std_logic; Y0 : out std_logic; Y1 : out std_logic; Y2 : out std_logic; Y3 : out std_logic; Y4 : out std_logic; Y5 : out std_logic; Y6 : out std_logic; Y7 : out std_logic);end decoder_3_8;architecture Behavioral of decoder_3_8 issignal YT0,YT1,YT2,YT3,YT4,YT5,YT6,YT7,check:std_logic;beginYT0=not(not S2) nand (not S1) nand (not S0);YT1=not(not S2) nand (not S1) nand S0;YT2=not(not S2) nand S1) nand (not S0);YT3=not(not S2) nand S1) nand S0;YT4=not(S2 nand (not S1) nand (not S0);YT5=not(S2 nand (not S1) nand S0;YT6=not(S2 nand S1) nand (not S0);YT7=not(S2 nand S1) nand S0;check=not(not(G1 nand (not G2A) nand (not G2B);Y0=(not YT0) nand check;Y1=(not YT1) nand check;Y2=(not YT2) nand check;Y3=(not YT3) nand check;Y4=(not YT4) nand check;Y5=(not YT5) nand check;Y6=(not YT6) nand check;Y7=(not YT7) nand check;end Behavioral;引脚锁定文件#PINLOCK_BEGINNET S2 LOC = P46;NET S1 LOC = P45;NET S0 LOC = P44;NET G2B LOC = P43;NET G2A LOC = P42;NET G1 LOC = P41;NET Y7 LOC = P90;NET Y6 LOC = P89;NET Y5 LOC = P88;NET Y4 LOC = P87;NET Y3 LOC = P86;NET Y2 LOC = P83;NET Y1 LOC = P82;NET Y0 LOC = P81;#PINLOCK_END2、8-3编码器实验代码library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity coder_8_3 is Port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; I5 : in std_logic; I6 : in std_logic; I7 : in std_logic; F0 : out std_logic; F1 : out std_logic; F2 : out std_logic);end coder_8_3;architecture Behavioral of coder_8_3 isbeginF0=(not I0) and (not I1) and (not I2) and (not I3) and I4 and (not I5) and (not I6) and (not I7)or(not I0) and (not I1) and (not I2) and (not I3) and (not I4) and I5 and (not I6) and (not I7)or(not I0) and (not I1) and (not I2) and (not I3) and (not I4) and (not I5) and I6 and (not I7)or(not I0) and (not I1) and (not I2) and (not I3) and (not I4) and (not I5) and (not I6) and I7);F1=(not I0) and (not I1) and I2 and (not I3) and (not I4) and (not I5) and (not I6) and (not I7)or(not I0) and (not I1) and (not I2) and I3 and (not I4) and (not I5) and (not I6) and (not I7)or(not I0) and (not I1) and (not I2) and (not I3) and (not I4) and (not I5) and I6 and (not I7)or(not I0) and (not I1) and (not I2) and (not I3) and (not I4) and (not I5) and (not I6) and I7);F2=(not I0) and I1 and (not I2) and (not I3) and (not I4) and (not I5) and (not I6) and (not I7)or(not I0) and (not I1) and (not I2) and I3 and (not I4) and (not I5) and (not I6) and (not I7)or(not I0) and (not I1) and (not I2) and (not I3) and (not I4) and I5 and (not I6) and (not I7)or(not I0) and (not I1) and (not I2) and (not I3) and (not I4) and (not I5) and (not I6) and I7);end Behavioral;引脚锁定文件#PINLOCK_BEGINNET I7 LOC = P48;NET I6 LOC = P47;NET I5 LOC = P46;NET I4 LOC = P45;NET I3 LOC = P44;NET I2 LOC = P43;NET I1 LOC = P42;NET I0 LOC = P41;NET F2 LOC = P83;NET F1 LOC = P82;NET F0 LOC = P81;#PINLOCK_END3、 优先编码的8-3编码器实验代码library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity coder_8_3_2 is Port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; I5 : in std_logic; I6 : in std_logic; I7 : in std_logic; F0 : out std_logic; F1 : out std_logic; F2 : out std_logic);end coder_8_3_2;architecture Behavioral of coder_8_3_2 isbeginprocess(I0,I1,I2,I3,I4,I5,I6,I7)beginif I7=1 thenF0=1;F1=1;F2=1;elsif I6=1 thenF0=1;F1=1;F2=0;elsif I5=1 thenF0=1;F1=0;F2=1;elsif I4=1 thenF0=1;F1=0;F2=0;elsif I3=1 thenF0=0;F1=1;F2=1;elsif I2=1 thenF0=0;F1=1;F2=0;elsif I1=1 thenF0=0;F1=0;F2=1;elsif I0=1 thenF0=0;F1=0;F2=0;elseF0=0;F1=0;F2=0;end if;end process;end Behavioral;引脚锁定文件#PINLOCK_BEGINNET I7 LOC = P48;NET I6 LOC = P47;NET I5 LOC = P46;NET I4 LOC = P45;NET I3 LOC = P44;NET I2 LOC = P43;NET I1 LOC = P42;#NET I0 LOC = P41;NET F2 LOC = P83;NET F1 LOC = P82;NET F0 LOC = P81;#PINLOCK_END实验二 七段显示译码器的设计实验要求1 设计一个BCD-7段显示译码器。输入输出ABCDC0C1C2C3C4C5C600001111110000101100000010110110100111111001010001100110101101101101101011111011111100001000111111110011110011101XXXXXXXX11XXXXXXXXX2 把上述译码器扩展到16进制-7段译码器，即增加对A、B、C、D、E、F的显示。实验目的1、 进一步熟悉四变量的卡诺图的化简，练习用组合逻辑设计的一般方法解决实际问题。2、 学习BCD-7段显示译码器的设计方法。实验过程和讨论1、 由于真值表已经给出，是4变量的布尔函数，所以可以用卡诺图手工化简输出的布尔函数，化简结果如下所示：这些函数用基本的与门、或门和非门就可以很容易实现。2、 16进制-7段译码器的真值表如下所示：输入输出ABCDC0C1C2C3C4C5C600001111110000101100000010110110100111111001010001100110101101101101101011111011111100001000111111110011110011101011101111011001111011001001110110101111011110100111111111000111有上述真值表可以得到各个输出所对应的布尔函数如下：显然，有上述的布尔函数，通过与门、或门和非门就能得到对应的结果。本实验中比较困难的是引脚锁定的问题，需要首先观察每个开关所对应的数字键盘上灯的位置，然后进行相应的锁定才能够得到想要的效果。设计完毕。实验代码和引脚锁定1、BCD-7段译码器实验代码library ieee;use ieee.std_logic_1164.all;entity bcd_7 isport(A,B,C,D:in std_logic;C0,C1,C2,C3,C4,C5,C6:out std_logic);end bcd_7;architecture data_flow of bcd_7 isbeginC0=A or (B and D) or C or (not B) and (not D);C1=A or (not C) and (not D) or (C and D) or (not B);C2=A or B or (not C) or D;C3=(not B) and (not D) or (not D) and C) or (B and (not C) and D) or (C and (not B);C4=(not B) and (not D) or (not D) and C);C5=A or (not C) and (not D) or (not D) and B) or (not C) and B);C6=A or (not D) and C) or (not C) and B) or (C and (not B);end data_flow;引脚锁定文件#PINLOCK_BEGINNET D LOC = P44;NET C LOC = P43;NET B LOC = P42;NET A LOC = P41;NET C0 LOC = P90;NET C1 LOC = P89;NET C2 LOC = P88;NET C3 LOC = P87;NET C4 LOC = P86;NET C5 LOC = P83;NET C6 LOC = P82;#PINLOCK_END2、16进制-7段译码器实验代码library ieee;use ieee.std_logic_1164.all;entity bcd_7_2 isport(A,B,C,D:in std_logic;C0,C1,C2,C3,C4,C5,C6:out std_logic);end bcd_7_2;architecture data_flow of bcd_7_2 isbeginC0=(B and C) or (not A) and C) or(A and(not D) or(not B) and (not D) or(not A) and B and D) or (A and (not B) and (not C);C1=(not B) and (not D) or (not B) and (not C) or (not A) and C and D) or (A and (not C) and D) or (not A) and (not C) and (not D);C2=(not C) and D) or (not A) and D) or (A and (not B) or (not A) and B) or (not B) and (not C);C3=(not A) and C and (not D) or (not B) and C and D) or (B and (not C) and D) or (A and B and (not D) or (not B) and (not C) and (not D);C4=(C and (not D) or (A and C) or (A and B) or (not B) and(not D);C5=(A and C) or (A and (not B) or (B and (not D) or (not C) and (not D) or (not A) and B and (not C);C6(S1,S0)Cn，这个顺序也就是if语句判断的先后顺序，运用if语句的嵌套功能即可以把逻辑描述清楚。在具体的每种运算的实现中，借助VHDL的ieee.std_logic_unsigned.all库函数里对于向量的相关操作既可以轻易实现。在这里比较特殊的一点就是，在两个8位的向量进行相加减的时候，如果产生进位，进位会被丢掉，不能保存下来，而这个进位又是题目要求的输出中的一个。解决办法是利用VHDL语句中的&操作符。比如对于长度为8的向量A，进行0&A运算，可以让A的长度增加一位，这样在和另一个长度为8的向量进行加或减运算的时候，进位可以被保存在新增加的那一位中，然后输出到输出。设计完成。实验代码及引脚锁定1、 全加器的实现实验代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY adder ISPort(A,B,CI:IN Bit; S,CO:OUT Bit);END adder;ARCHITECTURE behavior OF adder ISBEGINCO=NOT(B NAND CI) NAND (A NAND CI) NAND (A NAND B);S=NOT(NOT(NOT(NOT(A) NAND NOT(B) NAND CI) NAND (NOT(NOT(A) NAND B) NAND NOT(CI) NAND (NOT(A NAND NOT(B) NAND NOT(CI) NAND (NOT(A NAND B) NAND CI);END behavior;引脚锁定文件#PINLOCK_BEGINNET CI LOC = P43;NET B LOC = P42;NET A LOC = P41;NET CO LOC = P82;NET S LOC = P81;#PINLOCK_END2、 包含超前进位电路的四位全加器实验代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY FastAdder ISPort(A0,A1,A2,A3,B0,B1,B2,B3,CI:IN BIT; S0,S1,S2,S3,SO:OUT BIT);END FastAdder;ARCHITECTURE behavior OF FastAdder ISSIGNAL G0,G1,G2,G3,P0,P1,P2,P3,C1,C2,C3:BIT;BEGING1=A1 AND B1;G2=A2 AND B2;G3=A3 AND B3;G0=A0 AND B0;P1=A1 XOR B1;P2=A2 XOR B2;P3=A3 XOR B3;P0=A0 XOR B0;C1=G0 OR (P0 AND CI);C2=G1 OR (P1 AND G0) OR (P1 AND P0 AND CI);C3=G2 OR (P2 AND G1) OR (P2 AND P1 AND G0) OR (P2 AND P1 AND P0 AND CI);SO=G3 OR (P3 AND G2) OR (P3 AND P2 AND G1) OR (P3 AND P2 AND P1 AND G0) OR (P3 AND P2 AND P1 AND P0 AND CI);S0=P0 XOR CI;S1=P1 XOR C1;S2=P2 XOR C2;S3=P3 XOR C3;END behavior;引脚锁定文件：#PINLOCK_BEGINNET CI LOC = P49;NET B0 LOC = P48;NET B1 LOC = P47;NET B2 LOC = P46;NET B3 LOC = P45;NET A0 LOC = P44;NET A1 LOC = P43;NET A2 LOC = P42;NET A3 LOC = P41;NET S0 LOC = P87;NET S1 LOC = P86;NET S2 LOC = P83;NET S3 LOC = P82;NET SO LOC = P81;#PINLOCK_END3、 算术逻辑单元ALU实验代码library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity alu is Port ( M,Cn:in std_logic; A,B:in std_logic_vector(7 downto 0); S:in std_logic_vector(1 downto 0); C:out std_logic_vector(7 downto 0); Co:out std_logic );end alu;architecture Behavioral of alu issignal temp:std_logic_vector(8 downto 0);begindata_flow: process(M,Cn,A,B,S)beginif(M=0) thenif(S=00) thenC=not A;Co=0;elsif(S=01) thenC=A and B;Co=0;elsif(S=10) thenC=A or B;Co=0;elseC=A xor B;Co=0;end if;elseif(S=00) thenif(Cn=0) thentemp=0&A+B;elsif(Cn=1) thentemp=0&A+B+00000001;end if;C=temp(7 downto 0);Co=temp(8);elsif(S=01) thenif(Cn=0) thentemp=0&A-B;elsif(Cn=1) thentemp=0&A-B-00000001;end if;C=temp(7 downto 0);Co=temp(8);elseC=00000000;Co=0;end if;end if;end process data_flow;end Behavioral;引脚锁定文件：#PINLOCK_BEGINNET M LOC = P70;NET S LOC = P69;NET S LOC = P68;NET Cn LOC = P67;NET B LOC = P63;NET B LOC = P62;NET B LOC = P61;NET B LOC = P60;NET B LOC = P59;NET B LOC = P58;NET B LOC = P57;NET B LOC = P49;NET A LOC = P48;NET A LOC = P47;NET A LOC = P46;NET A LOC = P45;NET A LOC = P44;NET A LOC = P43;NET A LOC = P42;NET A LOC = P41;NET C LOC = P110;NET C LOC = P90;NET C LOC = P89;NET C LOC = P88;NET C LOC = P87;NET C LOC = P86;NET C LOC = P83;NET C LOC = P82;NET Co LOC = P81;#PINLOCK_END实验四 触发器和寄存器实验要求1、 用VHDL语言描述带异步清零和异步置数的D触发器。2、 用VHDL语言描述74LS175，编译并实现其逻辑功能。3、 用VHDL语言描述74LS194，编译并实现其逻辑功能。实验目的1、 练习用VHDL语言进行时序逻辑的设计。熟悉VHDL语言中时钟事件的描述。2、 熟悉D触发器的工作原理。3、 练习通过阅读器件手册来了解器件的逻辑功能。实验过程1、 D触发器的激励表如下：QnQn+1D000011100111其特征函数为：Qn+1=D，所以其基本的逻辑功能已经可以实现了。在题目中要求这个D触发器带有异步清零和异步置数功能，这个可以通过在process的敏感表中加入SET和CLR两个输入，在process内部，首先判断这两个输入是否有效，如果有效那么执行相关操作，不用判断是否处于时钟上升沿。这样就可以让这两个控