多功能数字钟课程设计整点报时与闹钟功能VHDL代码.doc

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity timkeeper is Port ( up,setpin,upclk,settime,run : in std_logic; a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0); result: out std_logic);end timkeeper;architecture Behavioral of timkeeper is component h_m_s_time port( clk0,clk1,ce : in std_logic; sec0,sec1 : buffer std_logic_vector(3 downto 0); lock : in std_logic_vector(2 downto 0); up : in std_logic; min0,min1 : buffer std_logic_vector(3 downto 0); hour0,hour1 : buffer std_logic_vector(3 downto 0); ov : out std_logic ); end component; component date port( clk0,clk1,ce : in std_logic; lock : in std_logic_vector(2 downto 0); up : in std_logic; mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0); date0,date1 : buffer std_logic_vector(3 downto 0); ov : out std_logic ); end component; component month_year port( clk0,clk1,ce : in std_logic; lock : in std_logic_vector(2 downto 0); up : in std_logic; mon0,mon1 : buffer std_logic_vector(3 downto 0); year0,year1 : buffer std_logic_vector(3 downto 0) ); end component; component LED_disp port( lock : in std_logic_vector(2 downto 0); sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0); date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0); a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0) ); end component; component alarm Port ( hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0); settime,run : in std_logic; result : out std_logic);end component; signal Tlock:std_logic_vector(2 downto 0); signal Tsecond_wave:std_logic; signal Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1:std_logic_vector(3 downto 0); signal Tdate0,Tdate1,Tmon0,Tmon1,Tyear0,Tyear1:std_logic_vector(3 downto 0); signal Tovday,Tovmonth:std_logic; signal vcc:std_logic; begin vcc=1; process(setpin) begin if rising_edge(setpin) then Tlock=Tlock+1; end if; end process; u2:h_m_s_time port map(Tsecond_wave,upclk,vcc,Tsec0,Tsec1,Tlock,up, Tmin0,Tmin1,Thour0,Thour1,Tovday); u3:date port map(Tovday,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1, Tdate0,Tdate1,Tovmonth); u4:month_year port map(Tovmonth,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1); u5:LED_disp port map(Tlock,Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,Tdate0, Tdate1,Tmon0,Tmon1,Tyear0,Tyear1,a0,a1,b0,b1,c0,c1); u6:alarm port map (Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,settime,run ,result);end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;use work.pac.all;entity alarm is Port ( hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0); settime,run : in std_logic; result : out std_logic);end alarm;architecture Behavioral of alarm issignal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0);beginp0:process(settime) begin if settime=1then dhour1=hour1; dhour0=hour0; dmin1=min1; dmin0=min0; dsec1=sec1; dsec0=sec0; end if; end process p0;p1:process(run) begin if run=1then if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then result=1; else result=0; end if; else result=0; end if; end process p1;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;use work.pac.all;entity date is Port ( clk0,clk1,ce : in std_logic; lock : in std_logic_vector(2 downto 0); up : in std_logic; mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0); date0,date1 : buffer std_logic_vector(3 downto 0); ov : out std_logic);end date;architecture Behavioral of date is signal tempy0:std_logic_vector(1 downto 0); signal tempy1,clk:std_logic; signal Td0,Td1:std_logic_vector(3 downto 0); begin tempy0=year0(1 downto 0);tempy1=year1(0); Td0=date0;Td1=date1; u1:process(lock,clk0,clk1) begin if(lock=000 or lock=001) then clk=clk0; else clk=clk1; end if; end process u1; u2:process(clk,ce) begin if rising_edge(clk) then if(ce=1) then if(lock=000) or (lock=001) or (lock=100 and up=1) then if(mon0=0010 and mon1=0000) then Feb_add_day(Td0,Td1,tempy0,tempy1,date0,date1); elsif(mon0=0001 and mon1=0000) or (mon0=0011 and mon1=0000) or( mon0=0101 and mon1=0000) or(mon0=0111 and mon1=0000) or (mon0=1000 and mon1=0000) or(mon0=0000and mon1=0001) or (mon0=0010 and mon1=0001) then oddmonth_add_day(Td0,Td1,date0,date1); else evenmonth_add_day(Td0,Td1,date0,date1); end if; end if; if(lock=100 and up=0) then if(mon0=0010 and mon1=0000) then Feb_sub_day(Td0,Td1,tempy0,tempy1,date0,date1); elsif(mon0=0001 and mon1=0000) or (mon0=0011 and mon1=0000) or(mon0=0101 and mon1=0000) or (mon0=0111 and mon1=0000) or (mon0=1000 and mon1=0000) or(mon0=0000 and mon1=0001) or (mon0=0010 and mon1=0001) then oddmonth_sub_day(Td0,Td1,date0,date1); else evenmonth_sub_day(Td0,Td1,date0,date1); end if; end if; end if; end if; end process u2; u3:process(ce) begin if rising_edge(clk) then if(lock/=000 and lock/=001) then ov=0; elsif(ce=1) then if(mon0=0010 and mon1=0000) then if(tempy1=0 and tempy0=00) or (tempy1=1 and tempy0=10) then if(date0=1001 and date1=0010) then ov=1; else ov=0; end if; elsif(date0=1000 and date1=0010) then ov=1; else ov=0; end if; elsif(mon0=0001 and mon1=0000) or(mon0=0011 and mon1=0000) or (mon0=0010 and mon1=0000) or (mon0=0111 and mon1=0000)or (mon0=1000 and mon1=0000) or(mon0=0000 and mon1=0001) or (mon0=0010 and mon1=0001) then if(date0=0001 and date1=0011) then ov=1; else ov=0; end if; elsif(date0=0000 and date1=0011) then ov=1; else ov=0; end if; end if; end if; end process u3;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;use work.pac.all;entity h_m_s_time is Port ( clk0,clk1,ce : in std_logic; sec0,sec1 : buffer std_logic_vector(3 downto 0); lock : in std_logic_vector(2 downto 0); up : in std_logic; min0,min1 : buffer std_logic_vector(3 downto 0); hour0,hour1 : buffer std_logic_vector(3 downto 0); ov : out std_logic);end h_m_s_time;architecture Behavioral of h_m_s_time is signal Ts0,Ts1,Tm0,Tm1,Th0,Th1:std_logic_vector(3 downto 0); signal clk:std_logic;begin Ts0=sec0;Ts1=sec1;Tm0=min0;Tm1=min1;Th0=hour0;Th1=hour1; u1: process(lock,clk0,clk1) begin if(lock=000 or lock=001) then clk=clk0; else clk=clk1; end if; end process u1; u2: process(clk,lock) begin if rising_edge(clk) then if(ce=1) then if(lock=000)or(lock=001)or(lock=111 and up=1) then addsec_addmin(Ts0,Ts1,sec0,sec1); end if; if(lock=111 and up=0) then subsec_submin(Ts0,Ts1,sec0,sec1); end if; if(lock=000 or lock=001) then if(sec0=1001 and sec1=0101) then addsec_addmin(Tm0,Tm1,min0,min1); end if; if(sec0=1001 and sec1=0101 and min0=1001 and min1=0101) then addhour(Th0,Th1,hour0,hour1); end if; if(sec0=1001 and sec1=0101 and min0=1001 and min1=0101 and hour0=0011 and hour1=0010) then ov=1; else ov=0; end if; end if; if(lock=110 and up=1) then addsec_addmin(Tm0,Tm1,min0,min1); end if; if(lock=101 and up=0) then subsec_submin(Tm0,Tm1,min0,min1); end if; if(lock=101 and up=1) then addhour(Th0,Th1,hour0,hour1); end if; if(lock=101 and up=0) then subhour(Th0,Th1,hour0,hour1); end if; end if; end if; end process u2;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity LED_disp is Port ( lock : in std_logic_vector(2 downto 0); sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0); date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0); a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0);end LED_disp;architecture Behavioral of LED_disp isbeginprocess(lock,sec0,sec1,min0,min1,hour0,hour1,date0,date1,mon0,mon1,year0,year1) begin if(lock=000) then a0=sec0;a1=sec1;b0=min0;b1=min1;c0=hour0;c1=hour1; end if; if(lock=000) then a0=sec0;a1=sec1;b0=min0;b1=min1;c0=hour0;c1=hour1; end if; if(lock=001) then a0=date0;a1=date1;b0=mon0;b1=mon1;c0=year0;c1=year1; end if; if(lock=101) then a0=0000;a1=0000;b0=0000;b1=0000;c0=hour0;c1=hour1; end if; if(lock=110) then a0=0000;a1=0000;b0=min0;b1=min1;c0=0000;c1=0000; end if; if(lock=111) then a0=sec0;a1=sec1;b0=0000;b1=0000;c0=0000;c1=0000; end if; if(lock=010) then a0=0000;a1=0000;b0=0000;b1=0000;c0=year0;c1=year1; end if; if(lock=011) then a0=0000;a1=0000;b0=mon0;b1=mon1;c0=0000;c1=0000; end if; if(lock=100) then a0=date0;a1=date1;b0=0000;b1=0000;c0=0000;c1=0000; end if; end process;end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;use work.pac.all;entity month_year is Port ( clk0,clk1,ce : in std_logic; lock : in std_logic_vector(2 downto 0); up : in std_logic; mon0,mon1 : buffer std_logic_vector(3 downto 0); year0,year1 : buffer std_logic_vector(3 downto 0);end month_year;architecture Behavioral of month_year is signal Ty0,Ty1,Tm0,Tm1:std_logic_vector(3 downto 0); signal clk:std_logic;begin Ty0=year0;Ty1=year1;Tm0=mon0;Tm1=mon1;u1: process(lock,clk0,clk1) begin if(lock=000 or lock=001) then clk=clk0; else clk=clk1; end if; end process u1;u2:process(clk,ce) begin if rising_edge(clk) then if (ce=1) then if(lock=000)or(lock=001)or(lock=011 and up=1) then add_month(Tm0,Tm1,mon0,mon1); end if; if(lock=011 and up=0) then sub_month(Tm0,Tm1,mon0,mon1); end if; if(lock=000 or lock=001) then if(mon0=0010 and mon1=0001)then add_year(Ty0,Ty1,year0,year1); end if; end if; if(lock=010 and up=1)then add_year(Ty0,Ty1,year0,year1); end if; if(lock=010 and up=0)then sub_year(Ty0,Ty1,year0,year1); end if; end if; end if; end process u2; end Behavioral;library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; package pac is procedure add_year(oldyear0,oldyear1:in std_logic_vector; signal newyear0:out std_logic_vector; signal newyear1:out std_logic_vector);procedure add_month(oldmonth0,oldmonth1:in std_logic_vector; signal newmonth0:out std_logic_vector; signal newmonth1:out std_logic_vector);procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector; signal newmonth0:out std_logic_vector; signal newmonth1:out std_logic_vector);procedure sub_year(oldyear0,oldyear1:in std_logic_vector; signal newyear0:out std_logic_vector; signal newyear1:out std_logic_vector);procedure Feb_add_day(oldday0,oldday1:in std_logic_vector; ty0:in std_logic_vector(1 downto 0); ty1:in std_logic; signal newday0:out std_logic_vector; signal newday1:out std_logic_vector);procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector; ty0:in std_logic_vector(1 downto 0); ty1:in std_logic; signal newday0:out std_logic_vector; signal newday1:out std_logic_vector);procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector; signal newday0:out std_logic_vector; signal newday1:out std_logic_vector);procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector; signal newday0:out std_logic_vector; signal newday1:out std_logic_vector);procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector; signal newday0:out std_logic_vector; signal newday1:out std_logic_vector); procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector; signal newday0:out std_logic_vector; signal newday1:out std_logic_vector); procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector; signal newtime0:out std_logic_vector; signal newtime1:out std_logic_vector);procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector; signal newtime0:out std_logic_vector; signal newtime1:out std_logic_vector);procedure addhour(oldhour0,oldhour1:in std_logic_vector; signal newhour0:out std_logic_vector; signal newhour1:out std_logic_vector);procedure subhour(oldhour0,oldhour1:in std_logic_vector; signal newhour0:out std_logic_vector; signal newhour1:out std_logic_vector);end pac;package body pac IS procedure add_year(oldyear0,oldyear1:in std_logic_vector; signal newyear0:out std_logic_vector; signal newyear1:out std_logic_vector)is begin if(oldyear0=1001 and oldyear1/=1001)then newyear0=0000;newyear1=oldyear1+1; else newyear0=oldyear0+1; end if; if oldyear0=1001 and oldyear1=1001 then newyear0=0000; newyear1=0000; end if; end add_year; procedure add_month(oldmonth0,oldmonth1:in std_logic_vector; signal newmonth0:out std_logic_vector; signal newmonth1:out std_logic_vector)is begin if oldmonth0=0010 and oldmonth1=0001 then newmonth0=0001; newmonth1=0000; elsif oldmonth0=1001 then newmonth0=0000; newmonth1=oldmonth1+1; else newmonth0=oldmonth0+1; end if; end add_month; procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector; signal newmonth0:out std_logic_vector;signal newmonth1: out std_logic_vector) isbegin if oldmonth0=0001and oldmonth1=0000then newmonth0=0010;newmonth1=0001; elsif oldmonth0=0000 and oldmonth1=0001 then newmonth0=1001;newmonth1= oldmonth1-1;else newmonth0=oldmonth0-1;end if;if oldmonth0=0000 and oldmonth1=0000then newmonth0=0010;newmonth1=0001; end if; end sub_month;procedure sub_year(oldyear0,oldyear1:in std_logic_vector;signal newyear0: out std_logic_vector;signal newyear1: out std_logic_vector) is beginif oldyear0=0000then if oldyear1=0000then newyear1=1001;else newyear1= oldyear1-1; end if; newyear0=1001;else newyear0=ol