FLASH370i_系列CPLD芯片介绍（中英文翻译）.doc

FLASH370i系列CPLD芯片介绍这篇应用说明书涵盖以下内容：（1）对复杂可编程逻辑器件（CPLD）的综合描述；（2）对FLASH370i系列器件的总体介绍。CPLD 简介空间占用更少，性能提高，费用降低，CPLD这些因素使其将PLD的概念扩展到一个更高性能的水平上。在结构上，CPLD是由大量的可编程逻辑器件（PLD）及逻辑阵列块（LAB）组成的，这些结构通过可编程内部矩阵（PIM）连接在一起。因此CPLD性能的提高并非是通过增加输入项与乘积项的数量，增大体积来实现的。大量的逻辑阵列块（LAB）提供了与PLD可相比拟的速度，因为基本的传输路径是通过一个逻辑阵列块而且各个的乘积项矩阵与PLD矩阵相当。大量的LAB也提供了更高的集成度。一个CPLD所包含的LABs根据其大小，通常介于2到16之间。LABs除了由PIM连接之外，也由输入与输出宏单元及专用输入宏单元相连。图1，2分别为CPLD的总构成图与内部LB的结构图。LAB的结构元件包括：（1）阵列；（2）分配器；（3）宏单元。CPLD中的乘积项矩阵与PLD中的乘积项矩阵一样，所不同之处在于，前者的输入也可以是来自于PIM。乘积项分配器是CPLD中的一个新概念，在CPLD中乘积项并非是通过输入与输出引脚固定与宏单元的，而是能根据需要联到不同的宏单元上。这样的结果是更加有效的乘积项分配与更高的集成度。根据CPLD的不同，乘积项分配器的应用也不相同，这些将在FLASH370i系列器件特性一结中加以讲述。宏单元接收单个的乘积项分配器提供的输入，即数量不确定的乘积项相或。在一些宏单元中，输入信号与另一个可能是Q端回馈的信号进入一个二输入的异或门。这样便将D触发器配置成T触发器，对于如计数器等某些设计，后者将使其获得性能上的提高。经过异或门之后，宏单元可被配置成寄存器型，组合逻辑型或锁存型。有两种类型的宏单元，输入/输出型与隐藏型。一些特殊的宏单元不仅输入到输入/输出型宏单元而且也反馈到乘积项矩阵。隐藏型宏单元仅为乘积项矩阵提供反馈信号。PIM的功能是将可用资源的需要部分，所有来自LAB的输出及某些输入输出引脚分派给适当的LAB。有两种PIM的应用方法：矩阵型的连接与乘积项型的连接。图3显示了基于矩阵型连接的两个LAB之间的数据传输。在矩阵型的连接中，LAB的每个输出可以通过一存储单元联结到任意个输入项中。每个PIM输入项被指定到一个特殊的LAB或功能中作为LAB乘积项矩阵的输入信号。在本示例中，只显示了四个PIM输入项，两个进入LAB1，两个进入LAB2。每一个输入项都有一个感受器，可以探测逻辑电平，缓冲信号，提供驱动。由于每一个LAB输出可以联接到任意的PIM输入，内部连接是100%可连通的。而且绝不会限制器件适配逻辑的能力。一个宏单元的输出可以能够联接到一个或多个PIM输入项。与基于选择型的连接方式相比，将存储单元作为连接的最大不足之处是传输延迟。图4描述了基于选择型连接的两个LABS之间的数据通信通道。在多路选择型连接中，选择器将多个PIM输入项中的一个送入LAB。PIM输入项不同于矩阵型连接之处在于，他们是从n（n指输入的选择器的数目）个选择器中的一个输入的，而非是一个或门存储阵列的输出。进入选择器的输入是所有的LAB输出及特殊的输入端与输入/输出引脚。图3示出了由两个4-1选择器产生的两路PIM输入项。在这个例子里，LAB1中的宏单元2与LAB2中的宏单元2都有两种进入选择器的可能，其他的输入仅有一种。选择器越宽（选择器输入的数目），所需进入每个LAB的输入将成功布通，每个信号布通到LAB的可能性也越大。选择器变宽的劣势在于通过PIM的传输延迟增加，也增大了结构尺寸。基于选择型连通结构的应用因选择器规模而不同。FLASH370i型CPLDS的特点FLASH370i型CPLDS提供了从2个到8个LABs的密度。图5显示了有8个LABs的CY7C374i/5i结构图。偶数型的器件将一半的宏单元隐藏，使得在引脚一定的情况下获得最大的集成度。表1示例了一些器件。CPLD是属于粗粒结构的可编程逻辑器件。它具有丰富的逻辑资源(即逻辑门与寄存器的比例高)和高度灵活的路由资源。CPLD的路由是连接在一起的，而FPGA的路由是分割开的。FPGA可能更灵活，但包括很多跳线，因此速度较CPLD慢。 CPLD以群阵列（array of clusters）的形式排列，由水平和垂直路由通道连接起来。这些路由通道把信号送到器件的引脚上或者传进来，并且把CPLD内部的逻辑群连接起来。CPLD之所以称作粗粒，是因为，与路由数量相比，逻辑群要大得到。CPLD的逻辑群比FPGA的基本单元大得多，因此FPGA是细粒的.CPLD的功能块 CPLD最基本的单元是宏单元。一个宏单元包含一个寄存器(使用多达16个乘积项作为其输入)及其它有用特性。 因为每个宏单元用了16个乘积项，因此设计人员可部署大量的组合逻辑而不用增加额外的路径。这就是为何CPLD被认为是“逻辑丰富”型的。 宏单元以逻辑模块的形式排列(LB)，每个逻辑模块由16个宏单元组成。宏单元执行一个AND操作，然后一个OR操作以实现组合逻辑。每个逻辑群有8个逻辑模块，所有逻辑群都连接到同一个可编程互联矩阵。 每个群还包含两个单端口逻辑群存储器模块和一个多端口通道存储器模块。前者每模块有8，192b存储器，后者包含4，096b专用通信存储器且可配置为单端口、多端口或带专用控制逻辑的FIFO。 CPLD的好处之一是在给定的器件密度上可提供更多的I/O数，有时甚至高达70%。 时序模型简单 CPLD优于其它可编程结构之处在于它具有简单且可预测的时序模型。这种简单的时序模型主要应归功于CPLD的粗粒度特性。 CPLD可在给定的时间内提供较宽的相等状态，而与路由无关。这一能力是设计成功的关键，不但可加速初始设计工作，而且可加快设计调试过程。 粗粒CPLD结构的优点 CPLD是粗粒结构，这意味著进出器件的路径经过较少的开关，相应地延迟也小。因此，与等效的FPGA相比，CPLD可工作在更高的频率，具有更好的性能。 CPLD的另一个好处是其软件编译快，因为其易于路由的结构使得布放设计任务更加容易执行。 图6，7显示了乘积项矩阵，乘积项分配器，宏单元，及FLASH370i系列器件的输入/输出宏单元。每个LAB有36个输入，这使得其足可以处理32位的运算。80个标准的乘积项被提供给乘积项分配器，乘积项分配器可以为16个宏单元中的每一个分配0到16个乘积项。此外，6个特殊的乘积项也由乘积项矩阵生成。他们是一个异步复位，异步置位，和两组的乘积项输出使能。输出宏单元（图8）提供一组4输出控制选项：（1）来自一个输出使能（2）来自另一个输出使能的控制，（3）一直使能控制，（4）一直不使能控制。每一个LAB包含4个输出使能乘积项，两个控制上面的8个宏单元，另两个控制下面的8个宏单元。状态宏单元（图8）含有寄存器，触发器，或是组合电路传输数据的选择项。对于输入输出宏单元，另有一个输出优先级选择器在信号到达输入/输出宏单元前来提高性能。对于隐藏型宏单元，另有一个选择器可以将状态寄存器配置成一个输入寄存器。如果隐藏型宏单元被配置成一个输入，就不会从矩阵中分配到乘积项输入。在图8中，结构位C7可以从输入/输出引脚选择反馈信号输入到寄存器，进而取代了来自乘积项矩阵的输入。对于每一个LAB而言，都有一个异步复位，置位乘积项。无论是时钟信号，复位或置位信号都有优先级选择器。对于CY7C371i/372i 与CY7C373i/374i/375i系列器件，每一个宏单元分别可以在两个时钟与四个时钟中进行选择。在一个LAB中的所有宏单元都接受同一优先级的时钟信号，复位或置位信号。优先级可以在每一个LAB中单独配置。图8描述了输入/输出宏单元，输入/输出同隐藏型宏单元。图9与图10描述了输入/时钟及输入宏单元。输入宏单元提供了组合逻辑，门限逻辑，单寄存器，或双寄存器输入的灵活性。CY7C371i/372i系列器件有两个输入/时钟引脚和四个输入引脚。CY7C373i/374i/375i系列器件有四个输入/时钟引脚和两个输入引脚。为了增加灵活性，每个时钟都可配置成正的或负的优先级。为了全面了解FLASH370i乘积项分配器的操作过程，需要介绍乘积项分配器设计中的两个重要方面：乘积项分配与乘积项共享。分配是指将乘积项资源赋予宏单元。传统的PLD设计没有分配的灵活性。每一个宏单元都有其固定的，特定的乘积项输入。在许多的设计中，每一个宏单元要求的乘积项输入往往不同，这也就对为每个宏单元指定不同的乘积项提出了要求。乘积项共享指的是一个乘积项被多个宏单元所共用。不同宏单元的逻辑等式有时候包含了一样的最小项。将生成的这一乘积项由多个宏单元所共用而不是为每个宏单元都分别生成这一最小项，可以极大的提高其性能。图11是FLASH370i系列器件乘积项分配器的概念表示，乘积项分配器的功能如同一个分块的或阵列，他为每个宏单元提供0到16 个乘积项的相或。每一个乘积项都可以单独被分配与共享。这一结构在将某个宏单元的乘积项用做另一个宏单元的输入上有着一些优势。图12是MACH乘积项分配器的概念上的表示。他不能在宏单元之间共享乘积项。四个乘积项的每一个都只能布道一个宏单元。每四个一组的乘积项分配是粒度更高的布局，但不是也很有效。为了展现这一低效之处。考虑一个需要五个乘积项输入的宏单元。两个乘积项簇一共可以提供8个可能的乘积项输入。因为剩余的乘积项不能够再布通到其他的宏单元，这样就浪费了来自另一簇宏单元的3个乘积项资源。MAX7000型乘积项分配器示意图表现了扩展乘积项的应用（图13）。扩展项有两路通道通过矩阵，可以产生高效的应用。这些扩展项由LAB中的所有乘积项所共享。扩展项应用的不足之处在于两路通路通过矩阵时的延迟增加。这使得时间模型复杂化，也使得器件的性能与扩展乘积项的应用相联系。与MACH乘积项分配器相同，MAX7000型分配器也有五个乘积项簇。因而，当有多与一个簇连到某个宏单元时，同样会有乘积项浪费的问题。 FLASH370i乘积项分配器提供了最有效的乘积项分配与共享方案。信号通过乘积项分配器的传输与每一个宏单元的乘积项数目没有关系。PIM与乘积项分配器的灵活性使得无须改变器件引脚即可完成设计的修改。输入与输出的开关矩阵没有必要，那只会增加额外的延迟并降低器件的性能。FLASH370i系列器件的定时模式比其他的CPLD更加简单，这有以下两个原因。首先，所有进入LAB的输入信号都需通过PIM。这包括了所有的输入与输出，宏单元输出的反馈，及特定的输入。其次，通过乘积项分配器的延迟时间与分配给宏单元的乘积项数目无关。因此，没有扩展延迟，没有特定的输入/输出引脚延迟，也不会因使用了多达16个乘积项而性能降低，或是也不会因分配与扩展乘积项而有延迟。FLASH370i系列器件提供了可以像PLD一样的时间预测。FLASH370i系列器件的PIM被设计成达到100%的连通性，但也不会做的很宽以至影响到性能与尺寸。 The FLASH370i Family Of CPLDs This application note covers the following topics: (1) a general discussion of complex programmable logic devices (CPLDs),(2) an overview of the FLASH370i family of CPLDs.Overview of CPLDsCPLDs extend the concept of the PLD to a higher level of integration to improve system performance,use less board space, improve reliability, and reduce cost. Instead of making the PLD bigger with more input terms and product terms, a CPLDarchitecture is compo_ sed of multiple PLDs or logic blocks (LABs) connected together with a programmable interconnect matrix (PIM). Multiple Logic Array Blocks (LABs) provide comparable speed to a PLD because the basic propagation path is through one LAB and each LABs product term array is comparable to a PLD array. Multiple LABs provide the higher integration. The number of LABs in a CPLD is typically between 2 for the smaller CPLDs and 16 for the larger ones. In addition to LABs interconnected by the PIM, are the input/ output macrocells and the dedicated input macrocells. Figures 1 and 2 show the CPLD generic block diagram and the logic block diagram respectively. The architectural components of the LAB are: (1) the product term array, (2) the product term allocator, and (3) the macrocell. The product term array is the same in the CPLD as in the PLD except that the inputs into the array can now also come from the PIM. The product term allocator is a new concept in the CPLD where product terms are not fixed to a macrocell with its associated input/output pin but can be routed to different macrocells depending on where they are needed. The result is a more efficient allocation of product terms and higher integration. Implementation of the product term allocator varies across CPLD vendors which is more fully discussed in the section describing the features of the FLASH370i family. The macrocell accepts the single output of the product term allocator which is the ORing of a variable number of product terms. In some macrocells this input feeds into a two input XOR gate with the other input potentially carrying the Q feedback.This configures the D flip flop to a T flip flop which can provide an improvement in capacity for certain designs such as counters. After the XOR gate, the macrocell is configurable as registered, combinatorial, and in some cases latched. There are two kinds of macrocells which are input/output dedicated and buried. Dedicated macrocells output to the input/ output macrocell and also provide feedback into the product term array. Buried macrocells only provide feedback into the product term array. The function of the PIM is to distribute the needed fraction of the total available resources, all outputs from the LAB and possibly also dedicated inputs and inputs/outputs, to the appropriate LAB. There are two common methods of PIM implementation: array based interconnect and mux based interconnect. Figure 3 shows the data path of communication between two LABs using the array based interconnect. In the array based interconnect, each output of the LAB can potentially connect to any number of PIM input terms through a memory element.Each PIM input term is assigned to a specific LAB and functions as an input term into the LABs product term array. In this example only four PIM input terms are shown two going to LAB1 and two going to LAB2. There is a sense amp per input term to detect the logic level, buffer the signal, and drive it into the LAB. The true and complement of the PIM signal feed into the product term array (not shown in the figure). Since every LAB output can connect to any PIM input, the interconnect is considered 100 percent routable. It never limits the ability of the device to fit logic. A macrocell output can connect to one or multiple PIM input terms. The major drawback from using a memory element as an interconnect is the slower propagation delay than the muxed based interconnect. Figure 4 shows the data path of communication between two LABs using the muxed based interconnect. In the muxed based interconnect a mux chooses one of a number of potential PIM input terms into the LAB. The PIM input terms differ from the array based interconnect in that they are output from a 1 of n (where “n” is the number of inputs of the mux) mux instead of the output of a wired nor memory array. The inputs into the muxes are all the outputs of the LABs as well as dedicated inputs and input/output pins. Figure 3 shows two PIM input terms output from two 4-to-1 muxes. In this example, macrocell 2 from LAB1 and macrocell 2 from LAB2 both show 2 chances to route into the muxes with other inputs having only 1 chance. The wider the mux (the number of inputs into the mux) the more likely all desired inputs into each LAB will be successfully routed and the more chances each signal gets to route into a LAB. The disadvantage of larger muxes is a larger slower propagation delay through the PIM and increased die size. Implementations of mux-based interconnect vary in the size of the mux.Features of the FLASH370i CPLDsThe FLASH370i family of CPLDs offers densities from 2 to 8 LABs. Figure 5 shows the block diagram of the CY7C374i/5i with 8 LABs. The even numbers of the family (372i,374i) bury half of the macrocells for maximum integration with the same pinout as the (371i,373i,375i) respectively. Table 1 shows the family members offered. Figures 6 and 7 show the product term array, product term allocator, macrocells, and input/output macrocells for the FLASH370i family. Each LAB features 36 inputs, which can adequately handle 32-bit operations plus control signals with one pass through the LAB. The product term array features the true and complement polarities of each PIM output signal for a total of 72 inputs. 80 standard product terms are provided to the product term allocator which allocates from 0 to 16 product terms to each of the 16 macrocells. Additionally, 6 special product terms are also generated in the product term array. They are an asynchronous preset, asynchronous reset, and two groups of 2 bank output enable product terms. The output macrocell (Figure 8) provides a selection of four output controlling options: (1) control from one output enable;(2) control from a second output enable;(3) permanently enabled;(4) permanently disabled. Each LAB contains 4 output enable product terms, 2 for the upper 8 macrocells and 2 for the lower 8 macrocells. The state macrocell (Figure 8) contains options to register, latch, or send data through combinatorially. For the input/output macrocell there is an additional output polarity mux to improve capacity before the signal goes to the input/output macrocell. For buried macrocells there is an additional mux which can configure the state register as an input register. If the buried macrocell is configured as an input, zero product terms will be allocated from the array. In Figure 8 architecture bit C7 can choose the feedback from the input/output pin as the input into the register instead of from the product term array. There is one asynchronous preset and reset product term for each LAB. There are polarity muxes for the clocks, preset and reset. Each macrocell can choose among two clocking options for the CY7C371i/372i and four clocking options for the CY7C373i/374i/375i. All macrocells in a LAB receive the same polarity of the clock, set and reset. Polarities are configurable per LAB. Figure 8 shows the input/output macrocell and input/output plus buried macrocell. Figures 9 and 10 show the input/clock and input macrocells. The input macrocell provides the flexibility to let the input enter combinatorially, latched, single registered, or double registered (for maximum metastability performance). For the CY7C371i/372i there are two input/clocks pins and four input pins. For the CY7C373i/374i/375i there are four input/clock pins and two input pins. For added flexibility, each clock can be configurable for either positive or negative polarity. In order to fully understand the operation of the FLASH370i product term allocator, two important aspects of product term allocator design need to be introduced: product term steering and product term sharing. Steering refers to the assignment of a product term resource to a macrocell. In the traditional PLD there is no steering flexibility. Each macrocell has assigned product terms that can only be used by that macrocell. In many designs each macrocell requires a different number of product terms putting an emphasis on the ability to allocate product terms individually on an as needed basis. Product term sharing refers to a product term being used by multiple macrocells. The logic equations for different macrocells sometimes contain the same minterm. Instead of generating this same minterm multiple times, it is generated on only one product term and shared across macrocells, thereby improving capacity. Figure 11 is a conceptual representation of the FLASH370i product term allocator. The product term allocator functions like a segmented OR array by ORing from 0 to 16 product terms for each macrocell. Product terms can be steered and shared on an individual basis. This architecture has several advantages over other implementa_ tions that steer product terms away from one macrocell to serve another.CPLD can be quickly listed the CPLD structure is coarse-grained structure of the programmable logic device. It is rich in logic resources (ie logic gate with a high proportion of the Register) and the highly flexible routing resources. CPLD is linked to routing, and routing of the FPGA split open. FPGA may be more flexible, but including many of the jumper, the slow pace than CPLD. CPLD to-array (array of clusters) with the form, by the horizontal and vertical channel routing link. These routing channel signal to the pin on the device or Scientology, and to the logic of internal CPLD group linked up. CPLD has called coarse, because, in comparison with the routing number, the logical group to be large. CPLD logic FPGA group than the basic unit of much larger, FPGA is fine. CPLD CPLD function block is the most basic unit of Acer unit. A macro-element contains a register (using as many as 16 items as the product of its input), and other useful properties. Acer because each module of the 16 product items, So designers can deploy a large number of combinational logic without additional trails. This is why the CPLD is considered to be logical rich. Type. Acer unit in the form of logic module with (LB), each logic module from the 16-unit. Implementation of a macro-element AND operation, then an OR operation to achieve the combinational logic. Each group is the logic logic module 8, all groups are logically connected to the Internet with a programmable matrix. Each group also includes two single-port memory logic module and a multi-port memory access module. The former is 8 per module, memory 192b, which included four, 096b memory and dedicated communication can be configured as single-port and multi-port or with dedicated FIFO control logic. CPLD is one of the benefits to the density of the device can provide more I / O number, and sometimes even as much as 70%. CPLD simple sequential model is superior to other programmable structure is that it is simple and predictable time-series model. This simple sequential model must be attributed to the CPLD coarse-grained characteristics. CPLD in a given period of time for wider equal status, and had nothing to do with the routing. This capability is key to the success of the design, not only to accelerate the initial design work, but also to accelerate the design debugging process. Coarse-grained structure of the advantages of CPLD CPLD is coarse-grained structure, which means that the access device through the path less switch, corresponding to the delay also small. Thus, compared to equivalent FPGA, CPLD can work at a higher frequency, with better performance. CPLD Another advantage is that its software compiler fast, because of its easy routing architecture design tasks laid off more easy to implement.Figure 12 is a conceptual representation of the MACH product term allocator. It shows no ability to share product terms across macrocells. Each cluster of four product terms can route to only one macrocell. The product terms are routed in groups of four which is a much higher granularity of product term allocation and not as efficient.To demonstrate this inefficiency, consider a macrocell that needs five product terms to implement its logic. Two product term clusters with a total of eight available product terms are needed. This wastes the resources of three product terms from the borrowed cluster since these product terms can not be rerouted to another macrocell. TheMAX7000 product term allocator representation (Figure 13) shows the use of expander terms. Expander terms allow two passes thro