CPLD数字时钟；频率计；交通控制器；4＊4键盘扫描电路设计；8路跑马灯；数码管扫描电路设计；乒乓球游戏机；自动售货机；出租车计费器；电梯控制器的代码的代码.doc

数字时钟library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity clock isport(clk:in std_logic;-时钟输入 20mhz clr:in std_logic;-清零信号 en:in std_logic;-暂停信号 mode:in std_logic;-控制信号，用于选择模式 inc:in std_logic;-置数信号 seg7:out std_logic_vector(6 downto 0);-数码管显示信号 scan:out std_logic_vector(5 downto 0);-数码管扫描信号end;architecture one of clock is signal state:std_logic_vector(1 downto 0);-定义四种状态signal qhh,qhl,qmh,qml,qsh,qsl:std_logic_vector(3 downto 0);-小时、分、秒的高位和低位signal data:std_logic_vector(3 downto 0);signal cnt:integer range 0 to 5;-扫描数码管的计数器signal clk1khz,clk1hz,clk2hz:std_logic;-1khz、1hz、2hz的分频信号signal blink:std_logic_vector(2 downto 0);-闪烁信号signal inc_reg:std_logic;signal sec,min:integer range 0 to 59;signal hour:integer range 0 to 23;begin-1khz分频，用于扫描数码管地址process(clk)variable count:integer range 0 to 0;beginif clkevent and clk=1 then if count=0 then clk1khz=not clk1khz;count:=0; else count:=count+1; end if;end if;end process;-1Hz分频，用于计时process(clk1khz)variable count:integer range 0 to 1;beginif clk1khzevent and clk1khz=1 then if count=1 then clk1hz=not clk1hz;count:=0; else count:=count+1; end if;end if;end process;-2Hz分频，用于数码管闪烁process(clk1khz)variable count:integer range 0 to 0;beginif clk1khzevent and clk1khz=1 then if count=0 then clk2hz=not clk2hz;count:=0; else count:=count+1; end if;end if;end process;-模式转换process(mode,clr)beginif clr=1 then state=00;elsif modeevent and mode=1 thenstate=state+1;end if;end process;-状态控制process(clk1hz,state,en,clr,hour,sec,min)beginif en=1 then hour=hour;min=min;sec=sec;elsif clr=1 then hour=0;min=0;secif sec=59 then sec=0;-模式0，正常计时 if min=59 then min=0; if hour=23 then hour=0; else hour=hour+1;end if; else min=min+1;end if; else sec if inc=1 then -模式1，设定小时时间 if inc_reg=0 then inc_reg=1; if hour=23 then hour=0; else hour=hour+1; end if; end if; else inc_regif inc=1 then -模式2，设定分钟时间 if inc_reg=0 then inc_reg=1; if min=59 then min=0; else min=min+1; end if; end if; else inc_reg if inc=1 then -模式3，设定秒钟时间 if inc_reg=0 then inc_reg=1; if sec=59 then sec=0; else sec=sec+1; end if; end if; else inc_regblinkblinkclk2hz,others=0);when10=blinkclk2hz,others=0);when11=blinkclk2hz,others=0);end case;end process;-秒计数的十进制转BCD码-process(sec)begincase sec iswhen 0|10|20|30|40|50 =qslqslqslqslqslqslqslqslqslqslnull;end case;case sec is when 0|1|2|3|4|5|6|7|8|9 =qshqshqshqshqshqshnull;end case;end process;-分计数的十进制转BCD码-process(min)begincase min iswhen 0|10|20|30|40|50 =qmlqmlqmlqmlqmlqmlqmlqmlqmlqmlnull;end case;case min is when 0|1|2|3|4|5|6|7|8|9 =qmhqmhqmhqmhqmhqmhnull;end case;end process;-小时计数的十进制转BCD码-process(hour)begincase hour iswhen 0|10|20 =qhlqhlqhlqhlqhlqhlqhlqhlqhlqhlnull;end case;case hour is when 0|1|2|3|4|5|6|7|8|9 =qhhqhhqhhnull;end case;end process;-数码管动态扫描计数-process(clk1khz)beginif clk1khzevent and clk1khz=1 then if cnt=5 then cnt=0; else cnt data=qsl or (blink(0)&blink(0)&blink(0)&blink(0);scan data=qsh or (blink(0)&blink(0)&blink(0)&blink(0);scan data=qml or (blink(1)&blink(1)&blink(1)&blink(1);scan data=qmh or (blink(1)&blink(1)&blink(1)&blink(1);scan data=qhl or (blink(2)&blink(2)&blink(2)&blink(2);scan data=qhh or (blink(2)&blink(2)&blink(2)&blink(2);scannull;end case;end process; -七段译码-process(data)begincase data is when0000=seg7seg7seg7seg7seg7seg7seg7seg7seg7seg7seg7=0000000;end case;end process;end;频率计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cymometer isport(sysclk:in std_logic;-20mhz 时钟输入 clkin:in std_logic;-待测频率信号输入 seg7:out std_logic_vector(6 downto 0);-7段显示控制信号(abcdefg) scan:out std_logic_vector(7 downto 0);-数码管地址选择信号end;architecture one of cymometer issignal cnt:std_logic_vector(24 downto 0);-用于分频的计数器signal clk_cnt :std_logic;signal cntp1,cntp2,cntp3,cntp4,cntp5,cntp6,cntp7,cntp8:std_logic_vector(3 downto 0);signal cntq1,cntq2,cntq3,cntq4,cntq5,cntq6,cntq7,cntq8:std_logic_vector(3 downto 0);signal dat:std_logic_vector(3 downto 0);begin-0.5Hz分频-process(sysclk)beginif sysclkevent and sysclk=1 then if cnt=19999999 then clk_cnt=not clk_cnt;cnt0); else cnt=cnt+1; end if; end if;end process;-在一秒钟内计数-process(clkin)beginif clkinevent and clkin=1 then if clk_cnt=1 thenif cntp1=1001 then cntp1=0000; if cntp2=1001 then cntp2=0000; if cntp3=1001 then cntp3=0000; if cntp4=1001 then cntp4=0000; if cntp5=1001 then cntp5=0000; if cntp6=1001 then cntp6=0000; if cntp7=1001 then cntp7=0000; if cntp8=1001 then cntp8=0000; else cntp8=cntp8+1;end if; else cntp7=cntp7+1;end if; else cntp6=cntp6+1;end if; else cntp5=cntp5+1;end if; else cntp4=cntp4+1;end if; else cntp3=cntp3+1;end if; else cntp2=cntp2+1;end if;else cntp1=cntp1+1;end if; else if cntp1/=0000 or cntp2/=0000 or cntp3/=0000 or -对计数值锁存 cntp4/=0000 or cntp5/=0000 or cntp6/=0000 or cntp7/=0000 or cntp8/=0000 then cntq1=cntp1; cntq2=cntp2; cntq3=cntp3; cntq4=cntp4; cntq5=cntp5; cntq6=cntp6; cntq7=cntp7; cntq8=cntp8; cntp1=0000; cntp2=0000; cntp3=0000; cntp4=0000; cntp5=0000; cntp6=0000; cntp7=0000; cntp8scan=00000001;datscan=00000010;datscan=00000100;datscan=00001000;datscan=00010000;datscan=00100000;datscan=01000000;datscan=10000000;datnull;end case;end process;-数码管显示译码process(dat)begincase dat iswhen0000=seg7seg7seg7seg7seg7seg7seg7seg7seg7seg7null;end case;end process;end;交通控制器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jiao_tong isport(clk:in std_logic;-20mhz晶振时钟 jin:in std_logic;-禁止通行信号 scan:out std_logic_vector(1 downto 0);-数码管地址选择信号 seg7:out std_logic_vector(6 downto 0);-7段显示控制信号(abcdefg) ra,ya,ga:out std_logic;-主干道的红黄绿灯 rb,yb,gb:out std_logic);-支干道的红黄绿灯end;architecture one of jiao_tong istype states is(st1,st2,st3,st4);-四种状态signal clk1khz,clk1hz:std_logic;-分频信号包括1khz和1hzsignal one,ten:std_logic_vector(3 downto 0);-倒计时的个位和十位signal cnt:std_logic_vector(1 downto 0);-数码管扫描计数信号signal data:std_logic_vector(3 downto 0);signal seg7_temp:std_logic_vector(6 downto 0);signal r1,r2,g1,g2,y1,y2:std_logic;begin-1khz分频-process(clk)variable count:integer range 0 to 9999;beginif clkevent and clk=1 then if count=9999 then clk1khz=not clk1khz;count:=0; else count:=count+1; end if;end if;end process;-1hz分频-process(clk1khz)variable count:integer range 0 to 499;beginif clk1khzevent and clk1khz=1 then if count=499 then clk1hzif jin=0 then-状态st1，主干道通行35秒 if a=0 then qh:=0011;-高位为3 ql:=0100;-低位为4 a:=1; r1=0; y1=0; g1=1;-主干道绿灯亮 r2=1;-支干道红灯亮 y2=0; g2if jin=0 then -状态st2，主干道黄灯倒计时5秒 if a=0 then qh:=0000;-高位为0 ql:=0100;-低位为4 a:=1; r1=0; y1=1;-主干道黄灯点亮 g1=0; r2=1;-支干道红灯点亮 y2=0; g2if jin=0 then -状态st3，支干道通行25秒 if a=0 then qh:=0010;-高位为2 ql:=0100;-低位为4 a:=1; r1=1;-主干道红灯点亮 y1=0; g1=0; r2=0; y2=0; g2if jin=0 then -状态st4，支干道黄灯倒计时5秒 if a=0 then qh:=0000;-高位为0 ql:=0100;-低位为4 a:=1; r1=1;-主干道红灯点亮 y1=0; g1=0; r2=0; y2=1;-支干道绿灯点亮 g2=0; else if ql=1 then -如果倒计时结束则转到st1状态 stx:=st1; a:=0; qh:=0000; ql:=0000; else ql:=ql-1; end if; end if; end if;end case;end if;one=ql;ten=qh;end process;-禁止通行信号，数码管闪烁显示-process(jin,clk1hz,r1,r2,g1,g2,y1,y2,seg7_temp)beginif jin=1 then ra=r1 or jin;-主干道红灯点亮 rb=r2 or jin;-支干道红灯点亮 ga=g1 and not jin;gb=g2 and not jin;ya=y1 and not jin;yb=y2 and not jin;-实现显示闪烁seg7(0)=seg7_temp(0) and clk1hz;seg7(1)=seg7_temp(1) and clk1hz;seg7(2)=seg7_temp(2) and clk1hz;seg7(3)=seg7_temp(3) and clk1hz;seg7(4)=seg7_temp(4) and clk1hz;seg7(5)=seg7_temp(5) and clk1hz;seg7(6)=seg7_temp(6) and clk1hz;else seg7=seg7_temp;ra=r1;rb=r2;ga=g1;gb=g2;ya=y1;yb=y2;end if;end process;-数码管动态扫描计数-process(clk1khz)beginif clk1khzevent and clk1khz=1 then if cnt=01 then cnt=00; else cnt data=one;scan data=ten;scannull;end case;end process; -七段译码-process(data)begincase data is when0000=seg7_tempseg7_tempseg7_tempseg7_tempseg7_tempseg7_tempseg7_tempseg7_tempseg7_tempseg7_tempseg7_temp=1001111;-E显示，代表出错end case;end process;end; 4*4键盘扫描电路设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jp4x4_1 isport(clk:in std_logic;-扫描时钟信号 start:in std_logic;-开始信号，高电平有效 kbcol:in std_logic_vector(3 downto 0);-行扫描信号 kbrow:out std_logic_vector(3 downto 0);-列扫描信号 seg7_out:out std_logic_vector(6 downto 0);-7段显示信号(abcdefg) scan:out std_logic_vector(7 downto 0 );-数码管地址选择信号end;architecture one of jp4x4_1 is signal count:std_logic_vector(1 downto 0); signal sta:std_logic_vector(1 downto 0); signal seg7:std_logic_vector(6 downto 0); signal dat:std_logic_vector(4 downto 0); signal fn:std_logic;beginscan=00000001;-只使用一个数码管显示-循环描计数器process(clk)beginif clkevent and clk=1 then countkbrow=0001;stakbrow=0010;stakbrow=0100;stakbrow=1000;stakbrow=1111;end case;end if;end process;-行扫描译码process(clk,start)beginif start=0 then seg7 case kbcol is when 0001= seg7=1111001;dat s