nand_读写速度计算方法详解.docx

Nand Flash读写速度的计算方法在下面的部分，我们以Micron的Nand Flash芯片为例，看一下Nand Flash的访问速度(Write / Read)是如何计算的？我们可以利用Datasheet提供的Read / Program / Erase操作时序图进行逐项累加，并通过一定的公式推导来完成。以下图为例，这是一个相当复杂的图示。它包含两部分(target)。每个target有两个LUNs (Logic Unit)。每个都是完全独立的。但LUNs can do interleaved operations. 如下图所示：LUN1 和LUN2 在同一个target中。这样的好处是：最大化带宽和降低干扰。上述设备的参数具体情况如下：下面以Synchronous Interface为例进行Nand Flash访问速度的计算：1. Read operationRead a single page消耗时间计算如下:7 * tCAD (Send address and command) + (tWB + tR) (Read data from the NAND Flash Array into the data register) + tdqs * 4320(Transfer a page of data out)tCAD = 25nstWB = 100nstR = 25ustdqs = 0.5 tCK (minimum)tCK = 12ns (minimum)Total Time: 7 * 25ns + 100ns + 25000ns + 0.5 * 12ns * 4320 = 51195nsData Transferred: 4320 bytesBandwidth: 4320 bytes / 51.195us = 84.4MB/s主要特性:1) 页大小为: 4K + 224 Bytes。2) 采用DQS的上升沿和下降沿同时采集数据来进行传输。 2 LUN Four-plane page readThe time needed: (7 * tCAD + tWB + tDBSY) * 3 + (7 * tCAD + tWB + tDBSY) * 3 + (7 * tCAD + tWB) + (7 * tCAD + tWB + tR) + (7 * tCAD + tCCS + tDQSCK + tdqs * 4320) * 8Note:tCAD = 25nstWB = 100nstDBSY = 0.5us = 500nstR = 30us = 30000ns (for multi-plane read)tdqs = 0.5tCKtCK = 12nstCCS = 200nstDQSCK = 20nstTime = (175ns + 100ns + 500ns) * 3 + (175ns + 100ns + 500ns) * 3 + (175ns + 100ns) + (175ns + 100ns + 30000ns) + (175ns + 200ns + 20ns + 0.5 * 12ns * 4320) * 8 = 2325ns + 2325ns + 30550ns + 210520ns = 245720nsData transferred: 4320 * 4 * 2 = 34560bytesBandwidth: 34560 bytes / 245.720us = 140.6MB/s Device that has 2 independent targets每个target是完全独立的，因此相应的速度在理论上为倍数关系。此种情况下的访问速度为倍数关系: 2 * 140.6MB/s = 281.2MB/s.2. Program operationSingle program operation写操作的时间消耗为： 6 * tCAD (Send address and command) + tADL + tDQSS + tdqs * 4320(Transfer the data into the Flash) + tCAD (Program confirm command) + tWB + tPROG (Program the Flash Array time) = tCAD = 25nstADL = 70ns (Minimum)tDQSS = 0.75tCK(minimum)tdqs = 0.2tCK (minimum)tWB = 100nstPROG = 160ustCK = 12nstTime = 150ns + 70ns + 0.75tCK + 0.2tCK * 4320 + 25ns + 100ns + 160us = = 150ns + 70ns + 9ns + 10368 ns + 25ns + 100ns + 160000ns = 170728ns = 170.722usData transferred: 4320bytesBandwidth = 4320bytes / 170.722us = 25.3MB/s 2 LUN Four-plane program operation先送命令和数据到4 planes,然后执行写操作。整个写的时间消耗为:tCAD + 4 * tCAD + tADL + tDQSS + tdqs * 4320 + tCAD + tWB + tDBSY * 3 + tCAD + 4 * tCAD + tADL + tDQSS + tdqs * 4320 + tCAD + tWB + tCAD + 4 * tCAD + tADL + tDQSS + tdqs * 4320 + tCAD + tWB + tDBSY * 3 + tCAD + 4 * tCAD + tADL + tDQSS + tdqs * 4320 + tCAD + tWB + tPROG = = tCAD + 4 * tCAD + tADL + tDQSS + tdqs * 4320 + tCAD + tWB + tDBSY * 6 + tCAD + 4 * tCAD + tADL + tDQSS + tdqs * 4320 + tCAD + tWB * 2 +tPROGtCAD = 25nstADL = 70ns(Minimum)tDQSS = 0.75tCKtdq = 0.2tCKtCK = 12nstPROG = 160000nstDBSY = 500nstWB = 100nsTotal time needed: 125ns + 70ns + 0.75 * 12ns + 0.2 * 12ns * 4320 + 25ns + 100ns + 500ns * 6 + 125ns + 70ns + 0.75 * 12ns + 0.2 * 12ns * 4320 + 25ns + 100ns * 2 + 160000ns= 67182ns + 21376 + 160000ns = 248558nsData transferred: 4320 bytes * 4 * 2 = 34560 bytesBandwidth: 34560 bytes / 248.558 us = 139.0MB/sDevice that has 2 targets每个target是完全独立的，因此相应的速度在理论上为倍数关系。即：139.0 MB/s * 2 = 278.2MB/s3. Erase operationErase a single block (See Figure 78 at page 99)Erase的时间消耗为： 5 * tCAD (Send command and block address) + tWB + tBERS (Block erase time)tCAD = 25nstWB = 100nstBERS = 3ms tTime = 5 * 25ns + 100ns + 3000000ns = 3000225ns = 3000.225usData erased: 128 pages * 4320 bytes/page = 552960bytesBandwidth = 552960 bytes / 3000.225us = 184.3MB/s2 LUN Erase 4-plane block operation整个Erase操作的时间消耗为:(5 * tCAD + tWB + tDBSY) * 3 + (5 * tCAD + tWB) + (5 * tCAD + tWB + tDBSY) * 3 + (5 * tCAD + tWB + tBERS) = tCAD = 25nstWB = 100nstDBSY = 0.5us = 500nstBERS = 3ms = 3000000nstTime = 6 * (125ns + 100ns + 500ns) + (125ns + 100ns) * 2 + 3000000ns = 4350ns + 450ns +3000000ns = 3004800ns = 3004.800usData Erased: 2 * 128 pages * 4320 bytes/page * 4 planes = 4423680 bytesBandwidth = 4423680 bytes / 3004.8 us = 1472.2MB/sTwo target 4-plane erase operation每个target是完全独立的，因此相应的速度在理论上为倍数关系。即：2 * 1472.2MB/s = 2944.4 MB/s写状态：首先将坏块管理中的地址与当前块地址对照，排除无效块。 无效块读时钟置0，定义输出地址信号从输出地址端口输出 无效块读时钟置1，输出地址加1，将当前地址下的数据输出（此处的数据就是存储的无效块地址），判断如果坏块管理中心输出的坏块地址大于当前访问的块地址，则证明该地址为有效块（坏块肯定是少数，如果不是第一块则就是后面的，地址肯定大于当前有效块地址）命令80H或者81H之后写五个循环地址，之后等待一个ADL时间，然后将一页4K的数据从fifo中输入到flash中 读fifo时钟置1，保证fifo写地址大于读地址（此处fifo读地址就是我们当前flash的写地址），flash写有效，flash数据口输出当前fifo数据写完一个字节，读fifo时钟置0，也就是说在读fifo时钟为1的时候才能进行f