16_Control Unit

WilliamStallingsComputerOrganizationandArchitecture7thEdition,Chapter16ControlUnitOperation,Micro-Operations,AcomputerexecutesaprogramFetch/executecycleEachcyclehasanumberofstepsseepipeliningCalledmicro-operationsEachstepdoesverylittleAtomicoperationofCPU,Fetch-4Registers,MemoryAddressRegister(MAR)ConnectedtoaddressbusSpecifiesaddressforreadorwriteopMemoryBufferRegister(MBR)ConnectedtodatabusHoldsdatatowriteorlastdatareadProgramCounter(PC)HoldsaddressofnextinstructiontobefetchedInstructionRegister(IR)Holdslastinstructionfetched,FetchSequence,AddressofnextinstructionisinPCAddress(AR)isplacedonaddressbusControlunitissuesREADcommandResult(datafrommemory)appearsondatabusPCincrementedby1(inparallelwithdatafetchfrommemory)Data(instruction)movedtoIR,指令执行过程,指令执行过程举例：加法指令：oprs,rdrs1imm(disp)(rs)+主存数据rdrs1+disp,取指：存储器DBIR分析指令PCABADSW/R#=0M/IO#DBIRPC+1计算机数据地址：产生有效地址ARrsGR(rs)ALUdispALU+ALUAR到存储器取数ARABADSW/R#=0M/IO#=1DBDR,加法运算rsGR(rs)ALUDRALU+rdGRALUrd,控制信号一览表,JMP（rs1）+DispLOAD(rs1)+disp单元取数rs3.Storers(rs1)+Disp内存单元,JMP（rs1）+Disp1.取指PCABADS#W/R#=0M/IO#=1DBIRPC+1101010000000000000001102.计算机转移地址8104+132rs1GR(rs1)ALUDispALUALUPC010100010100100000000,LOAD(rs1)+disp单元取数rs1.取指2.计算地址81041319rs1GR(rs1)ALUdispALU+ALUAR0001000101001000001003.取数202123226ARABADS#W/R#=0M/IO#=1DBDR000001000000000000011104.数rs9121317rsGRDRALUdisp(0)ALU+ALUGR000000001001100010000,Storers(rs1)+Disp内存单元1.取指2.计算地址81041319rsGR(rs1)ALUDispALU+ALUAR0001000101001000001003.存数rsDR9111318rsGR(rs)ALUdisp(0)ALU+ALUDR0000000010101000010004.DR内存720212223DRDBARABADS#M/IO#=1W/R#=100000010000000000001111,微程序控制计算机的基本工作原理,微程序控制的基本概念微操作：一条指令的功能是通过按一定次序执行一系列基本操作完成的。微指令：由同时发出的控制信号所执行的一组微操作。微命令：组成微指令的微操作微程序：微指令序列的集合控制存储器：存放微程序ROM控制命令下一条微指令地址,实现微程序控制的基本原理,1.控制信号加法指令：每个控制信号一个控制位微指令格式：控制字段|下址字段2.微程序控制器,微程序设计技术,控制字段编译法：1.直接控制法：一位代表一个微命令微指令字长大2.字段直接编译法微周期：一条微指令所需的执行时间互斥微命令编成一组不发命令000:111,3.字段间接编译法：ABAB00100011:1111114.常数源字段EE给某些部件发送常数发射字段,某机有8条微指令，每条微指令所包含的微命令控制信号如下表所示：,a-j分别对应10种不同性质的微命令信号。假设一条微指令的控制字段为8位，请安排微指令的控制字段格式。,abcdeif,i,jf,ji,jf,hg,jf,jabcdeig,jf,habcdegi,jf,habcdegi,jf,h,微程序流的控制,微程序流的控制：当前微指令执行完毕后，怎样控制产生后继微指令的微地址。,1.产生后继微指令地址的方法,（1）以增量方式产生后继微地址顺序执行微指令时UPC+1转移类UPC与形成转移微地址的逻辑电路组合成后继微地址(2)增量与下址字段结合产生后继微地址控制字段|BCF|BAF转移地址字段转移控制字段转移时BAFUPC顺序UPC+1,（3）多路转移方式多路转移方式：一条微指令存在多个转移分支的情况（4）微中断：PROM控制存储器微程序控制器指令操作码,微指令入口地址,控制存储器容量为512*48（位），微指令字长为48位，微程序可以在整个控制存储器中实现转移，可控制转移的条件共4个（直接控制），微指令格式如下：微指令中的三个字段分别应为多少位？,某机的微指令格式中有10个独立的控制字段C0-C9，每个控制字段有Ni个互斥控制信号，Ni的值如下：(1)这10个控制字段，采用编码表示法，需要多少控制位?(2)如果采用直接控制编码方式，需要多少控制位？,InstructionCycle,Eachphasedecomposed(分解为）intosequenceofelementarymicro-operationsE.g.fetch,indirect,andinterruptcyclesExecutecycleOnesequenceofmicro-operationsforeachopcodeNeedtotiesequencestogetherAssumenew2-bitregisterInstructioncyclecode(ICC)designateswhichpartofcycleprocessorisin00:Fetch01:Indirect10:Execute11:Interrupt,FlowchartforInstructionCycle,FunctionalRequirements,DefinebasicelementsofprocessorDescribemicro-operationsprocessorperformsDeterminefunctionscontrolunitmustperform,BasicElementsofProcessor,ALURegistersInternaldatapathsExternaldatapathsControlUnit,TypesofMicro-operation,TransferdatabetweenregistersTransferdatafromregistertoexternalTransferdatafromexternaltoregisterPerformarithmeticorlogicalops,FunctionsofControlUnit,SequencingCausingtheCPUtostepthroughaseriesofmicro-operationsExecutionCausingtheperformanceofeachmicro-opThisisdoneusingControlSignals,ControlSignals,ClockOnemicro-instruction(orsetofparallelmicro-instructions)perclockcycleInstructionregisterOp-codeforcurrentinstructionDetermineswhichmicro-instructionsareperformedFlagsStateofCPUResultsofpreviousoperationsFromcontrolbusInterruptsAcknowledgements,ModelofControlUnit,ControlSignals-output,WithinCPUCausedatamovementActivatespecificfunctionsViacontrolbusTomemoryToI/Omodules,DataPathsandControlSignals,InternalOrganization,UsuallyasingleinternalbusGatescontrolmovementofdataontoandoffthebusControlsignalscontroldatatransfertoandfromexternalsystemsbusTemporaryregistersneededforproperoperationofALU,CPUwithInternalBus,Intel8085CPUBlockDiagram,Intel8085PinConfiguration,Intel8085OUTInstructionTimingDiagram,HardwiredImplementation(1),ControlunitinputsFlagsandcontrolbusEachbitmeanssomethingInstructionregisterOp-codecausesdifferentcontrolsignalsforeachdifferentinstructionUniquelogicforeachop-codeDecodertakesencodedinputandproducessingleoutputnbinaryinputsand2noutputs,HardwiredImplementation(2),ClockRepetitivesequenceofpulsesUsefulformeasuringdurationofmicro-opsMustbelongenoughtoallowsignalpropagation（传送）DifferentcontrolsignalsatdifferenttimeswithininstructioncycleNeedacounterwithdifferentcontrolsignalsfort1,t2etc.,ControlUnitwithDecodedInputs,ProblemsWithHardWiredDesigns,Complexsequencingµ-operationlogicDifficulttodesignandtestInflexibledesignDifficultto