buck 线路-single switching-2015

,Switchingregulatorsolution,FundamentalbuckcircuitdiagramMosfetPowerLossCapselect&considerpointChokeselect&considerpointStandardswitchingsolution(singlephase),Outline,Fundamentalbuckcircuitdiagram,If=100%,Po=Ps,1.StandardBuckregulator,2.Buckregulator应用及计算,H,H,VL(ON)=Vin-Vo=L(diL/dt)=diL/dt=(Vin-Vo)/L,VL(OFF)=-Vo=L(diL/dt)=diL/dt=-Vo/L,根據法拉第與伏秒定理.=VL(ON)*TON+VL(OFF)*TOFF=0,IfTON=D,TOFF=1-D,TON+TOFF=TS=VL(ON)*DT+VL(OFF)*(1-D)T=0=(Vin-Vo)/L*DT-(Vo/L)(1-D)T=0,=(Vin-Vo)/L*DT=(Vo/L)(1-D)T,=Vin*DVo*D=Vo*(1-D)=Vin*D=Vo-Vo*D+Vo*D,=Vin*D=Vo=D=Vo/Vin,3.Bootstrapcircuit,WhenLow_sideMOSFETturn-on,1.PVCCchargeCbootthroughRboottoground,2.TheCgsofMOSFETdischargethroughRgate,3.Sothefalling-timeofMOSFETdependonRgate,WhenHigh_sideMOSFETturn-on,1.Cboot通过Rboot&Rgate给High_sideMOSFETCgs充電,2.所以Rboot+Rgate越大，MOS的开通速度越慢，Rboot+Rgate越小，MOS的开通速度越快,Vin=5V,Vout=1.5V,AP70T03H,IPD06N03LG,Iout=10A,PVCC,Bootvoltage,4.BuckregulatorWaveformAnalysis,MosfetPowerLoss,1.HighSidePowerLoss:,Ploss=Pconduction+Pswitching+Pdriver+Poutput,Conductionloss,Switchingloss,其中：,Driverloss,OutputCaploss,2.LowSidePowerLoss:,Ploss=Pconduction+Pdriver+PDiode+Poutput,Conductionloss,Driverloss,Diodeloss,OutputCaploss,3.Highside与LowSidepowerlosscompare:,Capselect&considerpoint,1.Capacitordesignconsiderfactor,RatedvoltageCapacitancevalueRatedripplecurrentCasesizeESRValueLife(L=Lo*2exp(105-Ts)/10),2.Life,3.Capacitordesignconsider,Inputcapacitordesignconsidertheripplecurrent,inputcurrent,IIN,RMS=(Io/n)*nD*(1-nD)=(60/4)*4*0.108*(14*0.108)=7.43A,Example.,OutputcapacitordesignconsidertheESR&capacitorvalue.,4.Voltagedroopduetocapacitor,DropduetoESL,DropduetoESR,Dropduetocapacitance,5.Inputcapacitorwaveform,6.outputcapacitorwaveform,Chokeselect&Considerpoint,1.InputChoke&OutputChokedesignconsiderfactor,a.Corematerialselectb.Coilwireselectc.DCRranged.CalculateCoreloss&Coillosse.Costissue,2.Inductorripplecurrentcalculate,3.Transientwaveformsfordifferentinductorvalues,ForLessinductance-moreripplecurrent-moreoutputripplevoltage-increaseconductionloss-goodtransientresponse,Forhigherinductance-lowerripplecurrentandconductionlosses-largersizeinductors,4.Inductorselection,1)Lowerlimitisbasedonoutput-voltageripple,Forsinglephaseexample,Powersolutionrecommendsthattheripplevoltageshouldnotexceed50mVpeak-peak,2)Upperlimitisbasedonloadcurrentslew,Imax=20A,ESR=12mOHM,Baseon820uF/6.3V(ESR=36mOhm)*3,Sothemaxinductorperphaseis4.43uH,Standardswitchingsolution(singlephase),Placement,snubber,choke,D,D,S,HighsideMOSFET,I/Pcap,O/PCaps,Controller,S,RCsnubber,I/PChoke,Singlephase的solution主要是forchipset和Memory。对于Memory希望在DIMMslot的左右两侧及中间各放一只电容。为了降低output的ripplenoiseand平衡输出电容所承担的ripplecurrent，所以O/Pchoke后端必须放置可以承受经由O/Pchoke流出ripplecurrent的电容。,RgandRgsshouldbeplacedascloseaspossibletotheMOSFET,PlacementsummaryControllersection1.Controlleranditsownrelatedcomponents,whichshouldbeplacedascloseaspossibletothesocketofCPUandtheyshouldbebeyonda2CMdistancetotheO/PchokeandtheMOSFET.2.I/PcapsshouldbeplacedascloseaspossibletoeachhighsideMOSFET.3.EachhighsideMOSFETshouldgetaMLCCnearitsdrain.4.ThesourceofupperMOSFETandthedrainoflowerMOSFETshouldbeclosetotheO/Pinductorofthesamephase.5.ThermistorshouldbelocatedtothenearesthottestcomponentsuchasO/PchokeorMOSFET.6.AlltheMLCCofthecontrollershouldbelocatedtoclosewithcontroller.,SingleswitchingconsiderissuePHASEshapeplanVINshapeplanGNDofthesnubberGNDoftheLS_MOSGNDoftheInputMLCC,Layout,PWMICRefGND,Case1:originalplacement,Itsaswitchingcircuitfor+5V_DUALtotransform+1.8V_DUALOntheTOPlayer，the+1.8V_PHASEshapeistooapproachsuperIOOntheTOPlayer，theGNDofsnubberistooapproachsuperIO,Case1:modifyplacement,Changeoutputchoke、HS_MOSandLS_MOSplacementontheTOPlayerAdjustthe+1.8V_PHASEshapetokeeplongergapswithsuperIOdeviceChangetheGNDofsnubberplacementontheTOPlayerTheGNDofsnubbermustbeapproachtheGNDofLS_MOS,Case2:originalplacement,Itsaswitchingcircuitfor+5V_DUALtotransform+1.8V_DUALThe+1.8V_PHASEshapedidnttolayontheVCClayerThe+1.8V_PHASEshapeistoolongandnarrow,Case2:modifyplacement,ChangeHS_MOSandLS_MOSplacementontheTOPlayerAdjust+1.8V_PHASEshapetokeepshortandfoursquareplanThe+1.8V_PHASEshapemustbetolayontheVCClayerThe+1.8V_PHASEshapemustbetolaythesameontheTOPlayerandtheVCClayerDiscusswithE.Ewhetheritsenoughfor3VplanontheVCClayerornot,Case3:originalplacement,Itsaswitchingcircuitfor+5Vtotransform+1.2VOnBOTTOMlayer,theVGAtracestocutacrossthe+5V_INshapeandtooapproach+1.2V_PHASEshape,Case3:modifyplacement,AllthepowercircuitchangeslightlytomoveupTheVGAtraceschangetopassthroughbythesideofthepowercircuit,Case4:originalplacement,Itsaswitchingcircuitfor+3VtotransformVTT_CPUOnBOTTOMlayer,theVGAtracestocutacrosstheGNDofInputMLCC(10UF/6.3V(0805)X5R),Case4:modifyplacement,ChangeInputMLCC(10UF/6.3V(0805)X5R)placementontheTOPlayer,Case5:originalplacement,Itsaswitchingcircuitfor+5Vtotransform+1.2VOntheTOPlayer，the+1.2V_PHASEshapeistooapproachClockdeviceOntheBOTTOMlayer，underthe+1.2V_PHASEshapehaveclocktraces,Case5:modifyplacement,ChangepowercircuitplacementfarawaytheclockdeviceontheTOPlayerAvoidingpowercircuittointerferencewithclockdevice,Case6:originalplacement,Itsaswitchingcircuitfor+5V_DUALtotransform+1.8V_DUALOntheTO