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毕业设计(论文)外文资料翻译系 别： 电子信息系 专 业： 通信工程 班 级： B100309 姓 名： 张 杨 学 号： B10030942 外文出处： 附 件： 1. 原文； 2. 译文 2014年03月An Introduction to the ARM 7 ArchitectureTrevor Martin CEng, MIEETechnical DirectorThis article gives an overview of the ARM 7 architecture and a description of its major features for a developer new to the device. Future articles will examine other aspects of the ARM architecture.Basic CharacteristicsThe principle feature of the ARM 7 microcontroller is that it is a register based load-and-store architecture with a number of operating modes. While the ARM7 is a 32 bit microcontroller, it is also capable of running a 16-bit instruction set, known as THUMB. This helps it achieve a greater code density and enhanced power saving. While all of the register-to-register data processing instructions are single-cycle, other instructions such as data transfer instructions, are multi-cycle. To increase the performance of these instructions, the ARM 7 has a three-stage pipeline. Due to the inherent simplicity of the design and low gate count, ARM 7 is the industry leader in low-power processing on a watts per MIP basis. Finally, to assist the developer, the ARM core has a built-in JTAG debug port and on-chip embedded ICE that allows programs to be downloaded and fully debugged in-system.In order to keep the ARM 7 both simple and cost-effective, the code and data regions are accessed via a single data bus. Thus while the ARM 7 is capable of single-cycle execution of all data processing instructions, data transfer instructions may take several cycles since they will require at least two accesses onto the bus (one for the instruction one for the data). In order to improve performance, a three stage pipeline is used that allows multiple instructions to be processed simultaneously.The pipeline has three stages; FETCH, DECODE and EXECUTE. The hardware of each stage is designed to be independent so up to three instructions can be processed simultaneously. The pipeline is most effective in speeding up sequential code. However a branch instruction will cause the pipeline to be flushed marring its performance. As we shall see later the ARM 7 designers had some clever ideas to solve this problem.Fig 1 ARM 3- Stage pipelineARM7 Programming ModelThe programmers model of the ARM 7 consists of 15 user registers, as shown in Fig. 3, with R15 being used as the Program Counter (PC). Since the ARM 7 is a load-and- store architecture, an user program must load data from memory into the CPU registers, process this data and then store the result back into memory. Unlike other processors no memory to memory instructions are available.Fig 2 Load And Store ArchitectureAs stated above R15 is the Program Counter. R13 and R14 also have special functions; R13 is used as the stack pointer, though this has only been defined as a programming convention. Unusually the ARM instruction set does not have PUSH and POP instructions so stack handling is done via a set of instructions that allow loading and storing of multiple registers in a single operation. Thus it is possible to PUSH or POP the entire register set onto the stack in a single instruction. R14 has special significance and is called the link register. When a call is made to a procedure, the return address is automatically placed into R14, rather than onto a stack, as might be expected. A return can then be implemented by moving the contents of R14 into R15, the PC. For multiple calling trees, the contents of R14 (the link register) must be placed onto the stack.Fig 3 User Mode Register ModelIn addition to the 16 CPU registers, there is a current program status register (CPSR). This contains a set of condition code flags in the upper four bits that record the result of a previous instruction, as shown in Fig 4. In addition to the condition code flags, the CPSR contains a number of user-configurable bits that can be used to change the processor mode, enter Thumb processing and enable/disable interrupts.Fig 4 Current Program Status Register and FlagsException And Interrupt ModesThe ARM 7 architecture has a total of six different operating modes, as shown below. These modes are protected or exception modes which have associated interrupt sources and their own register sets.User: This mode is used to run the application code. Once in user mode the CPSR cannot be written to and modes can only be changed when an exception is generated. FIQ: (Fast Interrupt reQuest) This supports high speed interrupt handling. Generally it is used for a single critical interrupt source in a system IRQ: (Interrupt ReQuest) This supports all other interrupt sources in a systemSupervisor: A protected mode for running system level code to access hardware or run OS calls. The ARM 7 enters this mode after reset Abort: If an instruction or data is fetched from an invalid memory region, an abort exception will be generated Undefined Instruction: If a FETCHED opcode is not an ARM instruction, an undefined instruction exception will be generated.The User registers R0-R7 are common to all operating modes. However FIQ mode has its own R8 -R14 that replace the user registers when FIQ is entered. Similarly, each of the other modes have their own R13 and R14 so that each operating mode has its own unique Stack pointer and Link register. The CPSR is also common to all modes. However in each of the exception modes, an additional register一the saved program status register (SPSR)，is added. When the processor changes the current value of the CPSR stored in the SPSR，this can be restored on exiting the exception mode.Fig 5 Full Register Set For ARM 7Entry to the Exception modes is through the interrupt vector table. Exceptions in the ARM processor can be split into three distinct types.(i) Exceptions caused by executing an instruction, these include software interrupts, undefined instruction exceptions and memory abort exceptions(ii) Exceptions caused as a side effect of an instruction such as a abort caused by trying to fetch data from an invalid memory region. (iii) Exceptions unrelated to instruction execution, this includes reset, FIQ and IRQ interrupts.In each case entry into the exception mode uses the same mechanism. On generation of the exception, the processor switches to the privileged mode, the current value of the PC+4 is saved into the Link register (R14) of the privileged mode and the current value of CPSR is saved into the privileged modes SPSR. The IRQ interrupts are also disabled and if the FIQ mode is entered, the FIQ interrupts are also disabled, Finally the Program Counter is forced to the exception vector address and processing of the exception can start. Usually the first action of the exception routine will be to push some or all of the user registers onto the stack.Fig 6 ARM 7 Vector TableA couple of things are worth noting on the vector table. Firstly, there is a missing vector at 0x000000014. This was used on an earlier ARM architecture and is left empty on ARM 7 to allow backward compatibility. Secondly, the FIQ interrupt is at the highest address so the FIQ routines could start from this address, removing the need for a jump instruction to reach the routine. It helps make entry into the FIQ routine as fast as possible.Once processing of the exception has finished, the processor can leave the privileged mode and return to the user mode. Firstly the contents of any registers previously saved onto the stack must be restored. Next the CSPR must be restored from the SPSR and finally the Program Counter is restored by moving the contents of the link register to R15, (i.e. the Program Counter). The interrupted program flow can then restart.Data TypesThe ARM instruction set supports six data types namely 8 bit signed and unsigned, 16 bit signed and unsigned plus 32 bit signed and unsigned. The ARM processor instruction set has been designed to support these data types in Little or Big-endian formats. However most ARM silicon implementations use the Little-endian format. ARM instructions typically have a three-operand format, as shown below ADD Rl，R2, R3 ; Rl=R2+R3ARM7 Program Flow ControlIn all processors there is a small group of instructions that are conditionally executed depending on a group of processor flags. These are branch instructions such as branch not equal. Within the ARM instruction set, all instructions are conditionally executable.Fig. 7 Instruction Condition Code BitsThe top four bits of each instruction contain a condition code that must be satisfied if the instruction is to be executed. This goes a long way to eliminating small branches in the program code and eliminating stalls in the pipeline so increasing the overall program performance. Thus for small conditional branches of three instructions or less, conditional execution of instructions should be used. For larger jumps, normal branching instructions should be used.Fig. 8 Instruction Condition CodesThus our ADD instruction below could be prefixed with a condition code, as shown. This adds no overhead to instruction execution EQADD R1，R2，R3 ;If(Zero flag = 1)then R1 = R2+R3The ARM7 processor also has a 32-bit barrel shifter that allows it to shift or rotate one of the operands in a data processing instruction. This takes place in the same cycle as the instruction. The ADD instruction could be expanded as follows EQADD R1，R2 R3，LSL #2 ; If ( Zero flag = 1) then R1 = R2+ (R3 x 4)Finally the programmer may decide if a particular instruction can set the condition code flags in the CPSR.EQADDS R1，R2 R3，LSL #2; If (Zero flag = 1) then R1 = R2 + (R3 x4)and set condition code flagsIn the ARM instruction set there are no dedicated call or return instructions. Instead these functions are created out of a small group of branching instructions. The standard branch (B) instruction allows a jump of around+-32Mb. A conditional branch can be formed by use of the condition codes. For example, a branch not equal would be the branching instruction B and the condition code NE for not equal giving BNE. The next form of the branch instruction is the branch with link.This is the branch instruction but the current value of the PC +4 is saved into R14, the link register. This acts as a CALL instruction by saving the return address into R14. A return instruction is not necessary since a return can be implemented by moving R14 into the PC. The return is more complicated in the case of an interrupt routine. Depending on the type of exception, it may be necessary to modify the contents of the link register to get the correct return address. For example, in the case of an IRQ or FIQ interrupt, the processor will finish its current instruction, increment the PC to the next instruction and then jumping to the vector table. This means that the value in the link register is PC+4 or one instruction ahead of the return address. This means we need to subtract 4 from the value in the link register to get the correct return address.This can be done in a single instruction thus:SUBS pc, r14, #4/ PC=Link register-4Fig 9 Branch and Branch Link Instruction OperationBranching instructions are also used to enter the 16-bit Thumb instruction set. Both the branch and branch-with-link may perform an exchange between 32-bit and 16-bit instruction sets and vice versa .The Branch exchange will jump to a location and start to execute 16-bit Thumb instructions. Branch link exchange will jump to a location, save PC+4 into the link register and start execution of 16-bit Thumb instructions. In both cases, the T bit is set in the CPSR. An equivalent instruction is implemented in the Thumb instruction set to return to 32-bit ARM instruction processing. Fig. 10 Branch Exchange and Branch Link Exchange Instruction OperationSoftware InterruptsThe ARM instruction set has a software interrupt instruction. Execution of this instruction forces an exception as described above; the processor will enter supervisor mode and jump to the SWI vector at 0x00000008. Fig. 11 Software Interrupt InstructionThe bit field 0-23 of the SWI instruction is empty and can be used to hold an ordinal. On execution of an SWI instruction, this ordinal can be examined to determine which SWI procedure to run and gives over 16 million possible SWI functions. Swi_ #1 . call swi function oneTn the swi handlerregister unsigned*link ptr asm (r14)； / define a pointer to the hnk registerSwitch (*(link-ptr-1)&Ox00FFFFFF) /calculate the number of the swi functionCase 0x01 : SWI_unction (); /Call the functionThis can be used to provide a hardware abstraction layer. In order to access OS calls or SFR registers, the user code must make a SWI call . All these functions are the running in a supervisor mode, with a separate stack and link register.As well as instructions to transfer data to and from memory and to CPU registers, the ARM 7 has instructions to save and load multiple registers. It is possible to load or save all 16 CPU registers or a selection of registers in a single instruction. Needless to say, this is extremely useful when entering or exiting a procedure.Fig. 12 Load and Store Multiple Instruction OperationThe CPSR and SPSR are only accessed by two special instructions to move their contents to and from a CPU register. No other instruction can act on them directly.Fig. 13 Programming The SPSR And CPSR RegistersTHUMB SupportThe ARM processor is capable of executing both 32-bit (ARM) instructions and 16- Bit (Thumb instructions). The Thumb instruction set must always be entered by running a Branch exchange or branch link exchange instruction and NOT by setting the T bit in the CPSR. Thumb instructions are essentially a mapping of their 32 bit cousins but unlike the ARM instructions, they are unconditionally executed except though for branch instructions.Fig. 14 Thumb Instruction ProcessingThumb instructions reduced number of only have unlimited access to registers RO-R7 and R13一Rl5. A instructions can access the full register set.Fig.15 Thumb programmers modelThe Thumb instruction set has the same load and store multiple instructions as ARM and in addition, has a modified version of these instructions in the form of PUSH and POP that implement a full descending stack in the conventional manner. The Thumb instruction set also supports the SWI instruction, except that the ordinal field is only 8 bits long to support 256 different SWI calls. When the processor is executing Thumb code and an exception occurs, it will switch to ARM mode in order to process the exception. When the CPSR is restored the, Thumb bit will be reset and the processor continues to run Thumb instructions.Fig.16 Thumb Exception ProcessingThumb has a much higher code density than ARM code, needing some 70% of the space of the latter. However in a 32-bit memory, ARM code is some 40% faster than Thumb. However it should be noted that if you only have 16-bit wide memory then Thumb code will be faster than ARM code by about 45%. Finally the other important aspect of Thumb is that it can use up to 30% less power than ARM code.ARM7的体系结构介绍特里沃马丁曾，鼠Technical Director技术总监本文给出了ARM 7架构的概述和开发新的设备，以及主要功能的描述，未来将研究ARM体系结构的其他方面。基本特点 ARM7单片机原理的特点是，它是一个基于寄存器的加载和存储与多个操作模式的体系结构。ARM7是一个32位单片机，它也能够运行16位指令集，被称为“拇指”。 这有助于实现一个更大的代码密度和加强节能。而所有的寄存器到寄存器的数据处理的指令都是单周期指令，如数据传送指令，多周期。增加这些指令的性能，ARM7具有三级管道。由于与低门数设计的固有的简单性，ARM7的低功耗处理在瓦/ MIP基础行业是领导者。最后，以协助开发，ARM内核有一个内置的JTAG调试端口和芯片上的“嵌入式冰”，允许程序被下载和全面调试系统。为了保持ARM既简单又划算，代码和数据区域通过单数据总线访问。因此ARM7能够单循环执行所有的数据处理指令，数据传送指令可能需要几个周期，因为他们将需要至少两个访问总线（一个是指令一个是数据）。为了提高性能，三个管道被用于允许多个指令同时处理。这个管道有三个阶段：接收，编译，执行。每一个阶段的硬件设计是独立的，三个指令能够同时地被执行。在迅速上升的连续代码中，此管道是最有效的。然而一个分支指令会导致管道的性能被破坏。我们必须看到后来的ARM7设计师提出一些聪明的办法来解决这些事情。图1 ARM7的三个阶段管道ARM 7程序设计模型程序设计员的ARM7模型由15个用户寄存器组成，如图3所示，R15被用做为程序设计器，自从ARM7作为下载和存储建筑学以后，用户程序必须从CPU暂存器下载数据，执行的数据和存储的结果返回到寄存器，不像其他的处理器没有记忆存储器指令可用。 图2 下载和存储体系结构如上所述，R15是程序计数器。R13和R14也有特殊功能：R13是被用作堆栈指针，尽管它仅仅被定义作为规划会议。不寻常的ARM7指令集没有push和pop指令，所以堆栈处理是通过一组指令,允许下载和在一个单一的操作多个寄存器存储，因此它可能是在整个寄存器组中push和pop堆栈上的一个单寄存器。R14具有特殊的意义，叫做“环节注册”。当访问到达程序时，返回地址自动的放入R14，而不是放入堆栈，正如所料。然后返回可以通过移动R14的内容到R15实现，PC机。对于多重的访问树，R14的内容必须被放置在堆栈。图3 用户模式注册模型除了16个CPU寄存器，还有一个现行程序状态寄存器，这包含一组条件代码旗上的四位，记录前一指令的结果，如图4所示。除了状态码标志，CPSR包含多个用户可配置的位，可以用来改变处理器模式，进入拇指模式处理和启用/禁用中断。图4 当前程序状态注册和标记异常和中断模式 ARM7体系结构模式有总数为6个不同的运行模式，如下面所示。这些模式被保护或者异常模式有相关的中断源和自己的寄存器组。用户模式：这个模式是用于运行代码应用。一旦在用户模式下的操作不能被写入和模式只能改变时，生成一个异常。快速中断模式：支持高速全速中断处理，通常在系统中用作单信号临界中断源。外部中断模式：支持系统中的所有中断源。管理模式：运行系统级别的代码访问硬件或者操作系统调用运行“保护”模式。ARM7复位后进入此模式。数据访问终止模式：如果一条命令或者数据从无效的记忆区域中取出，异常终止便产生。未定义指令：如果接收的操作码不是ARM指令，未定义的指令异常就会产生。用户寄存器R0-R7对所有的运行模式都是相同的。然而当进入快速中断模式后，快速中断模式有自己的R8-R14来代替用户寄存器。同样地，其他模式相互间有自己的R13和R14，以至于每一个运行模式有自己的唯一的堆栈指针和环节注册。CPSR对所有的模式共用。然而在每一个异常模式，额外的注册已保存的程序状态寄存器，被添加了。当处理器改变当前的CPSR，保存在SPSR，可以从异常模式中修复。图5 ARM7的全部寄存器组异常模式的进入是中断向量表的完成。异常在ARM处理器可以分为三个明显的类型。1、异常处理造成的原因是执行命令，包含软件中断，未定义指令异常和内存终止异常。2、异常处理造成的原因是指令的副作用，比如终止造成原因是尝试从无效内存区域接收数据。3、异常无关于执行指令，包含复位，快速中断和外部中断。在不同情况下的进入异常模式使用相同的原理。当异常发生，处理器切换到特权模式，当前的PC+4保存到注册环节（R14）的特权模式，CPSR的当前值保存到特权模式的SPSR。外部中断模式也被禁用，如果进入快速中断模式，快速中断模式也被禁用。最后程序计数器被迫开始异常向量地址和异常的处理。通常日常异常程序的第一步，就是向栈内堆入一些或者全部的用户寄存器。 图6 ARM7的矢量向量表向量表的几件事值得注意。第一，在0X000000014有缺失的向量，允许反向兼容性，过去常常被用在早期的ARM结构体系和被遗留下的空的ARM7中。第二，快速中断模式在最高地址，所以快速中断模式通常从这个地址开始，删除需要跳转指令实现例程。尽可能快的帮助进入快速中断模式。一旦异常处理已经完成，处理器就可以离开特权模式返回到用户模式。首先，任何寄存器以前保存的堆栈上