数字电路英文版-第七单元

CHAPTER7INTRODUCTIONTOPROGRAMMABLELOGICDEVICE,ABEL(件描述语言的一种)Architecture(结构体)Array(阵列)Buffer(缓冲器)Cell(单元)Compiler(编辑器)Documentationfile(使用说明文件)Fuse(熔丝)E2CMOS(电可擦除的CMOS)GAL(通用阵列逻辑器件)Inputfile(输入文件)Input/Output(I/O)(输入/输出),JEDECfile(标准数据格式文件)OLMC(输出逻辑宏单元)PAL(可编程阵列逻辑)PLA(可编程逻辑阵列)PLD(可编程逻辑器件)Programmer(编程器)PROM(可编程只读存储器)Software(软件)Synthesis(综合)Tristateoutputbuffer(三态输出缓冲器)ZIFsocked(不用力插座),KEYTERMS,ABELAdvancedBolleanExpressionLanguage.AsoftwarecompilerlanguageforPLDprogramming;atypeofhardwaredescriptionlanguage(HDL).ArchitectureTheinternalfunctionalarrangementoftheelementsthatgiveadeviceitsparticularoperatingcharacteristics.,ArrayInaPLD,amatrixformedbyrowsofproduct-termlinesandcolumnsofinputlineswithaprogrammablecellateachjunction.BufferAcircuitthatpreventsloadingofaninputoroutput.CellAfusedcrosspointofarowandcolumnninaPLD.,ComplierSoftwarethattranslatesfromhigh-levellanguagethatuseswordsorsymbols,suchasHDL,intolow-levelmachinelanguage(1sand0s).DocumentationfileTheinformationfromacomputerthatdocumentsthefinaldesignaftertheinputfilehasbeenprocessed.,E2CMOSElectricallyearsableCMOS(EECMOS).ThecircuittechnologyusedforthereprogrammablecellsinGAL.FuseTheprogrammableelementincertaintypesofPLDs;alsocalledafusiblelink.GALGenericarraylogic.APLDwithareprogrammableANDarray,afixedORarray,andprogrammableoutputlogicmacrocells.,InputfileTheinformationenteredinacomputerthatdescribeslogicdesignusingaPLDprogramminglanguagesuchasHDL.Input/Output(I/O)Aterminalofadevicethatcanbeusedaseitheraninputorasanoutput.,OLMCOutputlogicmarcocell.TheprogrammableoutputlogicinaGAL.PALProgrammablearraylogic.APLDwithaprogrammableANDarrayandafixedORarray.PLAProgrammablelogicarray.APLDwithaprogrammableANDandORarray.,PLDProgrammablelogicdevice.ProgrammerAninstrumentthatprogramsPLDusingaJEDECfiledownloadedfromacomputerrunningHDLsoftware.SoftwareComputerprograms;programsthatinstructacomputerwhattodoinordertocarryoutagivensetoftasks.,SynthesisThesoftwareprocessofconvertingacircuitdescriptiontoastandardJEDECfileforPLDprogramming.TristateoutputbufferAlogiccircuithavingthreeoutputstates:HIGH,LOW,andhighimpedance(open).,ZIFsocketZeroinsertionforcesocket.AtypeofsocketusedinmostprogrammersthatacceptsaPLDpackage.,7.1PLDARRAYSANDCLASSIFICATIONS,Programmablelogicdevices(PLDs)areusedinmanyapplicationstoreplaceSSIandMSIcircuits;theysavespaceandreducetheactualnumberandcostofdevicesinagivendesign.,2,APLDconsistofalargearrayofANDgatesandORgatesthatcanbeprogrammedtoachievespecifiedlogicfunctions.FourtypesofdevicesthatareclassifiedasPLDsaretheprogrammableread-onlymemory(PROM),theprogrammablelogicarray(PLA),theprogrammablearraylogic(PAL),andthegenericarraylogic(GAL).,3,ProgrammableArrays,TheORArray,A,A,B,B,X1,X2,X3,Fusiblelink,4,A,A,B,B,X1=A+B,X2=A+B,X3=A+B,5,TheANDArray,A,A,B,B,X1,X2,X3,6,A,A,B,B,X1=AB,X2=AB,X3=AB,7,ClassificationofPLDs,ProgrammableRead-OnlyMemory,FixedANDarray,ProgrammableORarray,Output1,Input1,Input2,Inputn,Output2,Outputm,8,ProgrammableLogicArray(PLA),ProgrammableANDarray,ProgrammableORarray,Output1,Input1,Input2,Inputn,Output2,Outputm,9,ProgrammableArrayLogic(PAL),ProgrammableANDarray,FixedORarrayandoutputlogic,Output1,Input1,Input2,Inputn,Output2,Outputm,10,GenericLogicArray(GAL),ProgrammableANDarray,FixedORarrayandProgrammableoutputlogic,Output1,Input1,Input2,Inputn,Output2,Outputm,11,7.2PROGRAMMABLEARRAYLOGIC(PAL),ThePALandtheGALarethemostcommonPLDsusedforlogicimplementation.Asyoulearnedinthelastsection,thePALinitsbasicformisaPLDwithaone-timeprogrammableANDarrayandfixedORarray.Inthissection,youwilllearnhowPALsareusedtoproducespecifiedcombinationallogicfunctionsandexamineaspecificPAL.,12,PALOperation(SOP),A,A,B,B,X,13,ImplementingaSum-of-ProductsExpressionX=AB+AB+AB,A,A,B,B,X,14,SimplifiedSymbols,A,A,B,B,X,A,B,4,AB,AB,AB,15,X,X,X,X,X,X,ProgrammableArrayLogic(PAL),ProgrammableANDarray,FixedORarray,Output1,Input1,Input2,Inputn,Output2,Input3,Outputm,Outputlogic,Outputlogic,Outputlogic,16,PALOutputCombinationLogic,Output,FromANDGatearray,Tristatecontrol,(a)Combinationoutput(active-LOW).,17,I/O,FromANDGatearray,Tristatecontrol,(b)Combinationinput/output(active-LOW).,18,I/O,FromANDGatearray,Tristatecontrol,(c)Programmablepolarityoutput,Programmablefuse,19,StandardPALNumbering,PAL10L8,Programmablearraylogic,Teninputs,Eightoutputs,Active-LOWoutput,20,7.3GENERICARRAYLOGIC(GAL),TheGALinitsbasicformisaPLDwithareprogrammableANDarray,afixedORarray,andprogrammableoutputlogic.Inthissection,basicconceptsareintroducedandSection7-4and7-5specificGALsareexamined.GALOperationelectricallyerasableCMOS(E2CMOS),21,A,A,B,B,X,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,E2CMOS,22,A,A,B,B,Off,On,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off,On,On,On,On,On,AB,AB,AB,X=AB+AB+AB,23,TheGALBlockDiagram,E2CMOSProgrammableANDarray,I/O1,Input1,Input2,Inputn,I/O2,Input3,I/Om,OLMC,OLMC,OLMC,24,StandardGALNumbering,GAL16V8,Genericarraylogic,Sixteeninputs,Eightoutputs,Variable-outputconfiguration,25,7.4THEGAL22V10,ThevariousGALsallhavethesametypeofprogrammablearray.Thedifferinthesizeofthearray,inthetypeofOLMCs,andinoperatingparameterssuchasspeedandpowerdissipation.Inthissection,apopulargenericarraylogicdevice,theGAL22V10,isdiscussed.,26,LogicDiagram,1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1,S0,S1,I/O,27,TheOutputLogicMacrocells(OLMCs)AsstatedinthediscussionofGALs,anOLMCcontainsprogrammablelogiccircuitsthatcanbeeitherforacombinationaloutputorinputorforaregisteredoutput.,28,1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1,S0,S1,I/O,(a)Active-LOWoutputS1=1,S0=0,29,1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1,S0,S1,I/O,(b)Active-HIGHoutputS1=1,S0=1,30,Input,Output,Tristate,control,HIGH,LOW,HIGH,Activestate,LOW,(a),HIGH,LOW,HIGH,Activestate,High-impedancestate,(b),31,OutputorInputSelection,1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1,S0,S1,HIGH,Output,(a)Output,32,1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1,S0,S1,LOW,Input,(b)Input,33,1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1=1,S0=1,S1=1,HIGH,X=ABCD+ABCD+ABCD+ABCD+ABCD+,X,ABCD,ABCD,ABCD,ABCD,ABCD,ABCD,ABCD,ActiveHIGH,RelatedProblemWritetheSOPexpressionfortheoutputifS0=0,S1=1,(ActiveLOW),1-of-4multiplexer,1-of-2multiplexer,Flip-Flop,OLMC,S1=1,S0=0,S1=1,HIGH,X=ABCD+ABCD+ABCD+ABCD+ABCD+ABCD,X,ABCD,ABCD,ABCD,ABCD,ABCD,ABCD,(ActiveLOW),Example7-6Showhowthefollowing6-variableSOPfunctionisimplementedwiththeAL22V10X=ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF,03,47,B,B,C,C,D,D,E,E,F,F,811,1215,1619,2023,4043,A,1,O,HIGH,S0=1,S1=1,OLMC,7.6PLDPROGRAMMING,Asyouhavelearned,PLAsareprogrammedbyleavingspecifiedfusiblelinksintactandblowingopenallothers.GALsareprogrammedinasimilarwayexcepttheE2CMOScellsareturnedonoroff.Thelogicfunctionstobeimplementeddetermineswhichcellsareaffected.,34,InordertoprogramaPLAorGAL,thefollowingitemsarerequired:acomputer,programmingsoftware,andaPLDprogrammer.,Computer:Anycomputerthatmeetsthesoftwareandprogrammerspecificationscanbeused.,35,Software:ThesoftwarepackagesforPLDprogrammingarecalledlogiccompliers.,TheProgrammer:TheprogrammerhasasoftwaredriverprogramthatreadsJEDECfilegeneratedbythelogiccomplierandconvertsittoinstructionsforapplyingrequiredvoltagestospecifiedPLDpinstoalterthespecifiedcellsinthearrayasdirectedbythefusemap.,36,START,Designthe,logiccircuit,Enterdesign,intocomputer,Syntaxor,Othererrors?,Complier,fileand,Design,simulation,Design,flaw?,processesinput,minimizeslogic,Debug,Edit,Yes,No,No,Yes,37,Compliercreates,JEDECfile(fusemap),Downloadto,programmer,Programmer“burns”,fusemapintoPLD,array,Compliergenerates,documentationfile,38,TheProgrammingProcess,EnteringtheDesign:Thelogicdesignisenteredintothecomputerbycreatinganinputorsourcefile.,RunningtheSoftware:Thesoftwarecomplierprocessesandtranslatestheinputfileandminimizesthelogic.,39,ProgrammingtheDevice:Whenthedesignisfinalized,thecompilercreatesafusemap(JEDECfile)anddownloadsittotheprogrammer.,40,7.7PLDSOFTWARE,Asmentionedearlier,thereareseveralsoftwarepackagesforimplementinglogicdesignsinPLDs.ABELiscommonlyusedhardwaredescriptionlanguages(HDLs).,41,IntroductiontoABEL:ABEL,whichistheacronymforAdvancedBooleanExpressionLanguage,allowslogicdesignstobeimplementedinprogrammableinprogrammablelogicdevices.,42,LogicDesignEntry:ABELprovidesthreedifferentformatsfordescribingandenteringalogicdesignfromthefromthecomputerkeyboard:equations,truthtables,andstatediagrams.,43,DesignSimulation:Oncealogiccircuitdesignhasbeenentered,itsoperationcanbesimulatedusingtestvectorstomakesuretherearenodesignerrors.,44,LogicSynthesis:Thesoftwareprocessofconvertingacircuitdescriptionintheformofequations,truthtables,orstatediagramstoastandardJEDECfileformatrequiredtoactuallyimplementthedesigninaPLDiscalledlogicsynthesis.,45