杭电 计组实验5-6-7(章老师不插板实验报告)

实验报告 2016年 5 月 10 日 成绩： 姓名学号班级专业计算机科学与技术课程名称计算机组成原理课程设计任课老师章复嘉指导老师章复嘉机位号实验序号5，6，7实验名称寄存器堆设计实验，MIPS汇编器与模拟器实验取，指令与译指令实验时间第6周第14周实验地点一教225实验设备号一、实验程序源代码实验五module main(input 0:0 wea,input 7:2 addra,output 31:0 douta,input Clk,Reset,input Write_Reg,input 4:0 W_Addr,input 31:0 W_Data,input 4:0 R_Addr_A,R_Addr_B,output 31:0 R_Data_A,R_Data_B );RAM A1( .clka(Clk), / input clka .wea(wea), / input 0 : 0 wea .addra(addra7:2), / input 5 : 0 addra .dina(R_Data_A), / input 31 : 0 dina .douta(douta) / output 31 : 0 douta);four B1( .Clk(Clk), .Reset(Reset), .Write_Reg(Write_Reg), .W_Addr(W_Addr), .W_Data(W_Data), .R_Addr_A(R_Addr_A), .R_Addr_B(R_Addr_B), .R_Data_A(R_Data_A), .R_Data_B(R_Data_B) );endmodulemodule RAM(input clka,input 0:0 wea,input 7:2 addra,input 31:0 dina,output 31:0 douta);RAM_B your_instance_name ( .clka(clka), / input clka .wea(wea), / input 0 : 0 wea .addra(addra7:2), / input 5 : 0 addra .dina(dina), / input 31 : 0 dina .douta(douta) / output 31 : 0 douta);endmodule#100;Reset=0;Clk=0;#100;W_Addr=5b11011;W_Data=32b11111111110001111111111101101111;Clk=0;#50;Clk=1;#100;R_Addr_A=5b11011;R_Addr_B=0;Clk=0;Write_Reg=0;#100;R_Addr_A=5b11011;Write_Reg=0;Clk=0;W_Addr=0;W_Data=0;#10;Clk=0;wea=1;addra=8b00110100;#10;Clk=1;#100;wea=0;addra=8b00110100;#100;Clk=0;#10;Clk=1;B#100;clka=0;wea=0;addra=6b000001;dina=32b11111111110001111111111101101111;#100;clka=1;wea=0;addra=6b000001;dina=32b11111111110001111111111101101111;#100;clka=0;wea=1;addra=6b000001;dina=32b11111111110001111111111101101111;#100;clka=1;wea=1;addra=6b000001;dina=32b11111111110001111111111101101111实验6nor $1,$0,$0; #$1=FFFF_FFFFsltu $2,$0,$1; #$2=0，000_0001add $3,$2,$2; #$3=0000_0002add $4,$3,$2; #$4=0000_0003add $5,$4,$3; #$5=0000_0005add $6,$5,$3; #$6=0000_0007sllv $7,$6,$2; #$7=0000_000Eadd $9,$5,$6; #$9=0000_000Csllv $8,$6,$9; #$8=0000_7000xor $9,$1,$8; #$9=FFFF_8FFFadd $10,$9,$1; #$10=FFFF_8FFEsub $11,$8,$7; #$11=0000_6FF2sub $12,$7,$8; #$12=FFFF_900Eadd $13,$9,$12; #$13=FFFF_200Dor $14,$9,$12; #$14=FFFF_9FFFor $15,$6,$7; #$15=0000_000Fnor $16,$5,$7; #$16=FFFF_FFF0add $17,$7,$3; #$17=0000_0010sllv $18,$8,$17; #$18=7000_0000sllv $19,$3,$17; #$19=0002_0000sllv $20,$19,$7; #$20=8000_0000sub $21,$1,$20; #$21=7FFF_FFFFor $22,$18,$21; #$22=7FFF_FFFFadd $23,$20,$22; #$23=FFFF_FFFFsub $24,$18,$19; #$24=6FFE_0000sub $25,$19,$18; #$25=9002_0000xor $26,$1,$18; #$26=8FFF_FFFFsltu $27,$22,$20; #$27=0000_0001sltu $28,$26,$20; #$28=0000_0000sub $29,$22,$2; #$29=7FFF_FFFEadd $30,$20,$2; #$30=8000_0001add $31,$11,$26; #$31=9000_6FF1实验7：module Inst(clk,rst,Inst_Code,PC_new,PC);input wire clk,rst;output wire 31:0 Inst_Code;output wire31:0 PC_new;output reg31:0 PC;initialbeginPC=32h0000_0000;endROM Inst_ROM( .addra(PC7:2), / input 5 : 0 addra.clka(clk), / input clka .douta(Inst_Code) / output 31 : 0 douta);assign PC_new=PC+4;always( negedge clk or posedge rst)beginif(rst)PC=32h0000_0000;else PC=24h000000,PC_new7:0;endendmoduleInst_ROM文件：memory_initialization_radix=16;memory_initialization_vector=00000827,0001102b,00421820,00622020,00832820,00a33020,00463804,00a64820,01264004,00284826,01215020,01075822,00e86022,012c6820,012c7025,00c77825,00a78027,00e38820,02289004,02239804,00f3a004,0034a822,0255b025,0296b820,0253c022,0272c822,0032d026,02d4d82b,0354e02b,02c2e822,0282f020,017af820;二、仿真波形实验五实验六实验七：三、电路图实验5实验7四、引脚配置