用VHDL语言设计闹钟系统

用VHDL语言设计闹钟系统(本实验用MAXPLUS2软件和GW48实验箱)课程设计题目：闹钟系统设计及实现目的与任务：1、巩固专业基础知识及EDA的相关知识；2、锻炼综合应用所学知识进行小型系统开发设计的能力；3、培养学生将理论应用于实践的能力；4、设计一个简单的闹钟系统。内容和要求：要求设计一个带闹钟功能的24小时计时器，计时器的外观如图1所示。图1 系统外观它包括以下几个组成部分： 显示屏：4个七段数码管显示当前时间(时：分)或设置的闹钟时间；一个发光二极管以1HZ的频率跳动，用于显示秒； 按键key1，用于设置调时还是调分； 按键key2，用于输入新的时间或新的闹钟时间，每按下一次，时或分加1； TIME(时间)键，用于确定新的时间设置； ALARM(闹钟)键，用于确定新的闹钟时间设置，或显示已设置的闹钟时间； 扬声器，在当前时钟时间与闹钟时间相同时，发出蜂鸣声。-key1输入作为计数器的触发信号 用来选择数码管LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY key1_trans_hjc IS PORT ( CLR_HJC: IN STD_LOGIC; KEY1_HJC: IN STD_LOGIC; Q_HJC : BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0);END ENTITY key1_trans_hjc IS;ARCHITECTURE HJC OF key1_trans_hjc IS BEGIN PROCESS(CLR_HJC,KEY1_HJC) IS BEGIN IF(CLR_HJC=1)THEN Q_HJC=000; ELSIF(KEY1_HJC=1 AND KEY1_HJCEVENT )THEN IF(Q_HJC=100)THEN Q_HJC=001; ELSE Q_HJC=Q_HJC+001; END IF; END IF; END PROCESS ;END ARCHITECTURE HJC;-key2用来设定由key1选中的数码管的值LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY KEY2_TRANS_HJC IS PORT ( CLR_HJC: IN STD_LOGIC; KEY2_HJC: IN STD_LOGIC; Q2_HJC : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY KEY2_TRANS_HJC;ARCHITECTURE ART OF KEY2_TRANS_HJC IS BEGIN PROCESS(CLR_HJC,KEY2_HJC) IS BEGIN IF(CLR_HJC=1)THEN Q2_HJC=0000; ELSIF(KEY2_HJC=1 AND KEY2_HJCEVENT )THEN IF(Q2_HJC=1001)THEN Q2_HJC=0000; ELSE Q2_HJC=Q2_HJC+0001; END IF; END IF; END PROCESS ;END ARCHITECTURE ART; -keybuffer_hjc实现选择数码管并赋值，LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY KEYBUFFER_HJC IS PORT (KEY1_CTRL_HJC: IN STD_LOGIC_VECTOR(2 DOWNTO 0); KEY2_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); CLK_HJC: IN STD_LOGIC; CLR_HJC: IN STD_LOGIC; NEW_TIME_0_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_TIME_1_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_TIME_2_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_TIME_3_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY KEYBUFFER_HJC ;ARCHITECTURE HJC OF KEYBUFFER_HJC IS SIGNAL N_T_0: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL N_T_1: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL N_T_2: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL N_T_3: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLR_HJC,CLK_HJC)IS BEGIN IF (CLR_HJC= 1)THEN N_T_0 = 0000; N_T_1 = 0000; N_T_2 = 0000; N_T_3 N_T_0 N_T_1 N_T_2 N_T_3 NULL; END CASE; END IF; END PROCESS ; NEW_TIME_0_HJC = N_T_0; NEW_TIME_1_HJC = N_T_1; NEW_TIME_2_HJC = N_T_2; NEW_TIME_3_HJC = N_T_3;END ARCHITECTURE HJC;-时钟256HZ，通过分频器FQ1_HJC产生1HZ用来驱动LED，以1HZ闪烁LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY FQ1_HJC IS PORT (CLK_IN_HJC: IN STD_LOGIC; CLR_HJC: IN STD_LOGIC; CLK_OUT1_HJC: OUT STD_LOGIC);END ENTITY FQ1_HJC ;ARCHITECTURE HJC OF FQ1_HJC IS BEGIN CLK1S: PROCESS(CLK_IN_HJC, CLR_HJC)IS SUBTYPE T_SHORT IS INTEGER RANGE 0 TO 65535; VARIABLE CNT1: T_SHORT; BEGIN IF (CLR_HJC= 1)THEN CNT1:= 0; CLK_OUT1_HJC = 0; ELSIF (RISING_EDGE(CLK_IN_HJC)THEN IF (CNT1 128)THEN CLK_OUT1_HJC = 1; CNT1:= CNT1+1; ELSIF (CNT1 256)THEN CLK_OUT1_HJC = 0; CNT1:= CNT1+1; ELSE CNT1:= 0; END IF; END IF; END PROCESS CLK1S;END ARCHITECTURE HJC;-时钟256HZ，通过分频器FQ_HJC产生1/60HZ用来驱动计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY FQ_HJC IS PORT (CLK_IN_HJC: IN STD_LOGIC; CLR_HJC: IN STD_LOGIC; CLK_OUT_HJC: OUT STD_LOGIC);END ENTITY FQ_HJC ;ARCHITECTURE HJC OF FQ_HJC IS BEGIN CLK1F: PROCESS(CLK_IN_HJC, CLR_HJC)IS SUBTYPE T_SHORT IS INTEGER RANGE 0 TO 65535; VARIABLE CNT: T_SHORT; BEGIN IF (CLR_HJC= 1)THEN CNT:= 0; CLK_OUT_HJC = 0; ELSIF (RISING_EDGE(CLK_IN_HJC)THEN IF (CNT 7680)THEN CLK_OUT_HJC = 1; CNT:= CNT+1; ELSIF (CNT 15360)THEN CLK_OUT_HJC = 0; CNT:= CNT+1; ELSE CNT:= 0; END IF; END IF; END PROCESS CLK1F ;END ARCHITECTURE HJC;-技术模块，没有新时间时，以24制时钟规律在计数，最小单位1分钟，有新时间时改变系统时间LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNTER_HJC IS PORT (NEW_CURRENT_TIME_0_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_CURRENT_TIME_1_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_CURRENT_TIME_2_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_CURRENT_TIME_3_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); LOAD_NEW_C_HJC: IN STD_LOGIC; CLK_HJC: IN STD_LOGIC; CLR_HJC: IN STD_LOGIC; CURRENT_TIME_0_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CURRENT_TIME_1_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CURRENT_TIME_2_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CURRENT_TIME_3_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY COUNTER_HJC ;ARCHITECTURE HJC OF COUNTER_HJC IS SIGNAL I_CURRENT_TIME_0: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL I_CURRENT_TIME_1: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL I_CURRENT_TIME_2: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL I_CURRENT_TIME_3: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS (CLK_HJC, CLR_HJC, LOAD_NEW_C_HJC)IS BEGIN IF (CLR_HJC = 1) THEN I_CURRENT_TIME_0 = 0000; I_CURRENT_TIME_1 = 0000; I_CURRENT_TIME_2 = 0000; I_CURRENT_TIME_3 = 0000; ELSIF (LOAD_NEW_C_HJC = 1) THEN I_CURRENT_TIME_0 = NEW_CURRENT_TIME_0_HJC; I_CURRENT_TIME_1 = NEW_CURRENT_TIME_1_HJC; I_CURRENT_TIME_2 = NEW_CURRENT_TIME_2_HJC; I_CURRENT_TIME_3 = NEW_CURRENT_TIME_3_HJC; ELSIF (RISING_EDGE(CLK_HJC)THEN IF (I_CURRENT_TIME_0 1001) THEN -分低位9 I_CURRENT_TIME_0 = I_CURRENT_TIME_0 +0001; ELSE I_CURRENT_TIME_0 = 0000; IF (I_CURRENT_TIME_1 0101)THEN -分高位5 I_CURRENT_TIME_1 = I_CURRENT_TIME_1 +0001; ELSE I_CURRENT_TIME_1 = 0000; IF (I_CURRENT_TIME_30010)THEN -时高位为0或1时 IF (I_CURRENT_TIME_21001)THEN -时低位9 I_CURRENT_TIME_2 = I_CURRENT_TIME_2 +0001; ELSE I_CURRENT_TIME_2 = 0000; I_CURRENT_TIME_3 = I_CURRENT_TIME_3 +0001; END IF; ELSE IF (I_CURRENT_TIME_20011)THEN -时高位为2时，时低位3 I_CURRENT_TIME_2 = I_CURRENT_TIME_2 +1; ELSE I_CURRENT_TIME_2 = 0000; I_CURRENT_TIME_3 = 0000; END IF; END IF; END IF; END IF; END IF; END PROCESS; CURRENT_TIME_0_HJC = I_CURRENT_TIME_0; CURRENT_TIME_1_HJC= I_CURRENT_TIME_1; CURRENT_TIME_2_HJC = I_CURRENT_TIME_2; CURRENT_TIME_3_HJC = I_CURRENT_TIME_3;END ARCHITECTURE HJC;-控制器，本系统有五个状态，S0-初始状态，S1-设置新时间状态 S2-确认为时钟时间状态，S3-确认为闹钟时间状态S4-显示闹钟时间状态，控制器就是控制状态转换的LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CONTROLLER_HJC IS PORT ( KEY1_HJC : IN STD_LOGIC; ALARM_BUTTON_HJC : IN STD_LOGIC; TIME_BUTTON_HJC : IN STD_LOGIC; CLK_HJC : IN STD_LOGIC; CLR_HJC : IN STD_LOGIC; LOAD_NEW_A_HJC : OUT STD_LOGIC; LOAD_NEW_C_HJC : OUT STD_LOGIC; SHOW_NEW_TIME_HJC : OUT STD_LOGIC; SHOW_A_HJC : OUT STD_LOGIC );END ENTITY CONTROLLER_HJC ISARCHITECTURE HJC OF CONTROLLER_HJC IS TYPE T_STATE IS(S0, S1, S2, S3, S4); SUBTYPE T_SHORT IS INTEGER RANGE 0 TO 65535; CONSTANT KEY_TIMEOUT : T_SHORT :=2560; -从按键状态返回时等待10S CONSTANT SHOW_ALARM_TIMEOUT : T_SHORT :=1280; -从闹钟时间返回时等待5S SIGNAL CURR_STATE : T_STATE; SIGNAL NEXT_STATE : T_STATE; SIGNAL COUNTER_K : T_SHORT; SIGNAL ENABLE_COUNT_K : STD_LOGIC; SIGNAL COUNT_K_END : STD_LOGIC; SIGNAL COUNTER_A : T_SHORT; SIGNAL ENABLE_COUNT_A: STD_LOGIC; SIGNAL COUNT_A_END : STD_LOGIC; BEGIN PROCESS(CLK_HJC, CLR_HJC) IS BEGIN IF (CLR_HJC = 1) THEN CURR_STATE = S0; ELSE IF (RISING_EDGE(CLK_HJC) THEN CURR_STATE = NEXT_STATE; END IF; END IF; END PROCESS; PROCESS (KEY1_HJC, ALARM_BUTTON_HJC, TIME_BUTTON_HJC, CURR_STATE, COUNT_A_END, COUNT_K_END) IS BEGIN NEXT_STATE = CURR_STATE; LOAD_NEW_A_HJC = 0; LOAD_NEW_C_HJC = 0; SHOW_A_HJC = 0; SHOW_NEW_TIME_HJC = 0; ENABLE_COUNT_K = 0; ENABLE_COUNT_A IF (KEY1_HJC = 1) THEN NEXT_STATE = S1; SHOW_NEW_TIME_HJC = 1; ELSIF (ALARM_BUTTON_HJC = 1)THEN NEXT_STATE = S4; SHOW_A_HJC = 1; ELSE NEXT_STATE IF (KEY1_HJC = 1)THEN NEXT_STATE = S1; ELSIF (ALARM_BUTTON_HJC =1)THEN NEXT_STATE = S2; LOAD_NEW_A_HJC = 1; ELSIF (TIME_BUTTON_HJC = 1)THEN NEXT_STATE = S3; LOAD_NEW_C_HJC = 1; ELSE IF(COUNT_K_END = 1)THEN NEXT_STATE = S0; ELSE NEXT_STATE = S1; END IF; ENABLE_COUNT_K = 1; END IF; SHOW_NEW_TIME_HJC IF (ALARM_BUTTON_HJC = 1)THEN NEXT_STATE = S2; LOAD_NEW_A_HJC = 1; ELSE NEXT_STATE IF (TIME_BUTTON_HJC = 1)THEN NEXT_STATE = S3; LOAD_NEW_C_HJC = 1; ELSE NEXT_STATE IF (KEY1_HJC = 1)THEN NEXT_STATE = S1; ELSE NEXT_STATE = S4; IF(COUNT_A_END = 1)THEN NEXT_STATE = S0; ELSE NEXT_STATE = S4; SHOW_A_HJC = 1; END IF; ENABLE_COUNT_A NULL; END CASE; END PROCESS; COUNT_KEY : PROCESS(ENABLE_COUNT_K, CLK_HJC)IS BEGIN IF (ENABLE_COUNT_K = 0)THEN COUNTER_K = 0; COUNT_K_END = KEY_TIMEOUT)THEN COUNT_K_END = 1; ELSE COUNTER_K = COUNTER_K + 1; END IF; END IF; END PROCESS COUNT_KEY; COUNT_ALARM : PROCESS(ENABLE_COUNT_A, CLK_HJC)IS BEGIN IF (ENABLE_COUNT_A = 0)THEN COUNTER_A = 0; COUNT_A_END = SHOW_ALARM_TIMEOUT)THEN COUNT_A_END = 1; ELSE COUNTER_A = COUNTER_A + 1; END IF; END IF; END PROCESS COUNT_ALARM;END ARCHITECTURE ;-显示驱动模块，是显示新时间还是闹钟时间，还是时钟时间LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DISPLAYDRIVER_HJC IS PORT(ALARM_TIME_0_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); ALARM_TIME_1_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); ALARM_TIME_2_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); ALARM_TIME_3_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); CURRENT_TIME_0_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); CURRENT_TIME_1_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); CURRENT_TIME_2_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); CURRENT_TIME_3_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_TIME_0_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_TIME_1_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_TIME_2_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_TIME_3_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); SHOW_NEW_TIME_HJC: IN STD_LOGIC; SHOW_A_HJC: IN STD_LOGIC; SOUND_ALARM_HJC: OUT STD_LOGIC; DISPLAY_0_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); DISPLAY_1_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); DISPLAY_2_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); DISPLAY_3_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY DISPLAYDRIVER_HJC;ARCHITECTURE HJC OF DISPLAYDRIVER_HJC IS SIGNAL DISPLAY_TIME_0: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL DISPLAY_TIME_1: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL DISPLAY_TIME_2: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL DISPLAY_TIME_3: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN CTRL: PROCESS(ALARM_TIME_0_HJC,ALARM_TIME_1_HJC,ALARM_TIME_2_HJC,ALARM_TIME_3_HJC, CURRENT_TIME_0_HJC,CURRENT_TIME_1_HJC,CURRENT_TIME_2_HJC,CURRENT_TIME_3_HJC, NEW_TIME_0_HJC,NEW_TIME_1_HJC,NEW_TIME_2_HJC,NEW_TIME_3_HJC, SHOW_A_HJC, SHOW_NEW_TIME_HJC)IS BEGIN IF NOT (ALARM_TIME_0_HJC = CURRENT_TIME_0_HJC AND ALARM_TIME_1_HJC = CURRENT_TIME_1_HJC AND ALARM_TIME_2_HJC = CURRENT_TIME_2_HJC AND ALARM_TIME_3_HJC = CURRENT_TIME_3_HJC)THEN SOUND_ALARM_HJC = 0; ELSE SOUND_ALARM_HJC = 1; END IF; IF (SHOW_NEW_TIME_HJC = 1)THEN DISPLAY_TIME_0 = NEW_TIME_0_HJC; DISPLAY_TIME_1 = NEW_TIME_1_HJC; DISPLAY_TIME_2 = NEW_TIME_2_HJC; DISPLAY_TIME_3 = NEW_TIME_3_HJC; ELSIF (SHOW_A_HJC= 1)THEN DISPLAY_TIME_0 = ALARM_TIME_0_HJC; DISPLAY_TIME_1 = ALARM_TIME_1_HJC; DISPLAY_TIME_2 = ALARM_TIME_2_HJC; DISPLAY_TIME_3 = ALARM_TIME_3_HJC; ELSIF (SHOW_A_HJC = 0)THEN DISPLAY_TIME_0 = CURRENT_TIME_0_HJC; DISPLAY_TIME_1 = CURRENT_TIME_1_HJC; DISPLAY_TIME_2 = CURRENT_TIME_2_HJC; DISPLAY_TIME_3 = CURRENT_TIME_3_HJC; ELSE ASSERT FALSE REPORT UNCERTAIN DISPLAY_DRIVER CONTROL! SEVERITY WARNING; END IF; END PROCESS CTRL; DISP: PROCESS(DISPLAY_TIME_0,DISPLAY_TIME_1,DISPLAY_TIME_2, DISPLAY_TIME_3)IS BEGIN DISPLAY_0_HJC = DISPLAY_TIME_0; DISPLAY_1_HJC = DISPLAY_TIME_1; DISPLAY_2_HJC = DISPLAY_TIME_2; DISPLAY_3_HJC = DISPLAY_TIME_3; END PROCESS DISP;END ARCHITECTURE;-GW48实验箱扬声器是脉冲驱动，在显示驱动模块产生高电平后与系统时钟相与得脉冲信号LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY YU_HJC ISPORT(ASOUNDIN_HJC :IN STD_LOGIC; CLK_HJC:IN STD_LOGIC; ASOUNDOUT_HJC:OUT STD_LOGIC);END ENTITY YU_HJC;ARCHITECTURE HJC OF YU_HJC IS BEGIN ASOUNDOUT_HJC= ASOUNDIN_HJC AND CLK_HJC;END ARCHITECTURE; -设置新闹钟时间LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ALARMREG_HJC IS PORT(NEW_ALARM_TIME_0_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_ALARM_TIME_1_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_ALARM_TIME_2_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); NEW_ALARM_TIME_3_HJC: IN STD_LOGIC_VECTOR(3 DOWNTO 0); LOAD_NEW_A_HJC: IN STD_LOGIC; CLK_HJC: IN STD_LOGIC; CLR_HJC: IN STD_LOGIC; ALARM_TIME_0_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ALARM_TIME_1_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ALARM_TIME_2_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ALARM_TIME_3_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY ALARMREG_HJC ;ARCHITECTURE HJC OF ALARMREG_HJC IS BEGIN PROCESS(CLK_HJC, CLR_HJC)IS BEGIN IF (CLR_HJC= 1)THEN ALARM_TIME_0_HJC = 0000; ALARM_TIME_1_HJC= 0000; ALARM_TIME_2_HJC= 0000; ALARM_TIME_3_HJC = 0000; ELSE IF(RISING_EDGE(CLK_HJC)THEN IF (LOAD_NEW_A_HJC = 1)THEN ALARM_TIME_0_HJC = NEW_ALARM_TIME_0_HJC; ALARM_TIME_1_HJC = NEW_ALARM_TIME_1_HJC; ALARM_TIME_2_HJC = NEW_ALARM_TIME_2_HJC; ALARM_TIME_3_HJC = NEW_ALARM_TIME_3_HJC; ELSIF (LOAD_NEW_A_HJC /= 0)THEN ASSERT FALSE REPORT UNCERTAIN LOAD_NEW_ALARM CONTROL! SEVERITY WARNING; END IF; END IF; END IF; END PROCESS;END ARCHITECTURE HJC;-顶层文件LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ALARM_HJC IS PORT (KEY1_HJC: IN STD_LOGIC; KEY2_HJC: IN STD_LOGIC; ALARM_BUTTON_HJC: IN STD_LOGIC; TIME_BUTTON_HJC: IN STD_LOGIC; CLK_HJC: IN STD_LOGIC; CLK1_HJC: OUT STD_LOGIC; CLR_HJC: IN STD_LOGIC; DISPLAY_0_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); DISPLAY_1_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); DISPLAY_2_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); DISPLAY_3_HJC: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SOUND_ALARM1_HJC: OUT STD_LOGIC);END ENTITY ALARM_HJC ;ARCHITECTURE HJC OF ALARM_HJC IS COMPONENT KEY1_TRANS_HJC IS PORT ( CLR_HJC: IN STD_LOGIC; KEY1_HJC: IN STD_LOGIC; Q_HJC : BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0); END COMPONENT ; COMPONENT KEY2_TRANS_HJC IS PORT ( CLR_HJ