VHDL基本逻辑电路设计

第6章基本逻辑电路设计,6.1组合逻辑电路设计6.2时序逻辑电路设计6.3存储器习题,6.1组合逻辑电路设计,6.1.1简单门电路1.2输入“与非”门,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYnand2ISPORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDnand2;ARCHITECTUREnand2_rtlOFnand2ISBEGINy=aNANDb;-NOT(aANDb)ENDnand2_rtl;,ARCHITECTUREnand2_behaveOFnand2ISBEGINPROCESS(a,b)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=a,数据流描述,行为描述,2.2输入“或非”门,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYnor2ISPORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDnor2;ARCHITECTUREnor2_rtlOFnor2ISBEGINy=aNORb;-NOT(aORb)ENDnor2_rtl;,ARCHITECTUREnor2_behaveOFnand2ISBEGINPROCESS(a,b)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=a,数据流描述,行为描述,3.反相器,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYinverterISPORT(a:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDinverter;ARCHITECTUREinverter_rtlOFinverterISBEGINy=NOTa;ENDinverter_rtl;,ARCHITECTUREinverter_behaveOFinverterISBEGINPROCESS(a)BEGINIF(a=1)THENy=0;ELSEy=1;ENDIF;ENDPROCESS;ENDinverter_behave;,数据流描述,行为描述,4.2输入“异或”门,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYxor2ISPORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDxor2;ARCHITECTURExor2_rtlOFxor2ISBEGINy=aXORb;ENDxor2_rtl;,ARCHITECTURExor_behaveOFxor2ISBEGINPROCESS(a,b)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=a,数据流描述,行为描述,6.1.2编、译码器与选择器1.3-8译码器,LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL;ENTITYdecoder3to8ISPORT(a,b,c,g1,g2a,g2b:INSTD_LOGIC;y:outstd_logic_vector(0to7);ENDdecoder3to8;ARCHITECTUREbehaveOFdecoder3to8ISSIGNALindata:STD_LOGIC_VECTOR(2DOWNTO0);BEGINindatayyyyyyyyy=“XXXXXXXX”;ENDCASE;ELSEy=“11111111”;ENDIF;ENDPROCESS;ENDbehave;,2.优先级编码器,常用于中断的优先级控制,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYpriorityencoderISPORT(input:INSTD_LOGIC_VECTOR(7DOWNTO0);y:OUTSTD_LOGIC_VECTOR(2DOWNTO0);ENDpriorityencoder;ARCHITECTUREbehaveOFpriorityencoderISBEGINPROCESS(input)BEGINIF(input(0)=0)THENy=“111”;ELSIF(input(1)=0)THENy=“110”;ELSIF(input(2)=0)THENy=“101”;ELSIF(input(3)=0)THENy=“100”;ELSIF(input(4)=0)THENy=“011”;ELSIF(input(5)=0)THENy=“010”;ELSIF(input(6)=0)THENy=“001”;ELSEy=“000”;ENDIF;ENDPROCESS;ENDbehave;,3.4选1选择器,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux4ISPORT(input:INSTD_LOGIC_VECTOR(3DOWNTO0);a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDmux4;ARCHITECTUREbehaveOFmux4ISSIGNALsel:STD_LOGIC_VECTOR(1DOWNTO0);BEGINsel=b,6.1.3加法器、求补器1.加法器(1)半加器,libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityhalf_adderisport(a,b:instd_logic;s,co:outstd_logic);endhalf_adder;architectureaofhalf_adderisbeginco=aandb;s=axorb;enda;,只有进位输出，没有进位输入,(2)全加器,libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfull_adderisport(a,b,cin:instd_logic;s,co:outstd_logic);endfull_adder;architectureaoffull_adderissignaltemp:std_logic_vector(1downto0);beginco=(aandb)or(aandcin)or(bandcin);s=axorbxorcin;enda;,2.求补器其逻辑关系应是：最高位符号位不变，余下的位取反，然后最低位加1。,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYcomplementISPORT(a:INSTD_LOGIC_VECTOR(7DOWNTO0);b:OUTSTD_LOGIC_VECTOR(7DOWNTO0);ENDcomplement;ARCHITECTUREaOFcomplementISBEGINPROCESS(a)VARIABLEtemp1:STD_LOGIC;VARIABLEtemp2:STD_LOGIC_VECTOR(6DOWNTO0);VARIABLEtemp3:std_logic_vector(7downto0);BEGINIF(a(7)=0)THENb=a;ELSEtemp1:=a(7);temp2:=NOTa(6downto0);temp3:=temp1,6.1.4三态门及总线缓冲器1.三态门,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtri_gateISPORT(din,en:STD_LOGIC;dout:STD_LOGIC);ENDtri_gate;ARCHITECTUREaOFtri_gateISBEGINPROCESS(din,en)BEGINIF(en=1)THENdout=din;ELSEdout=Z;ENDIF;ENDPROCESS;ENDa;,2.单向总线缓冲器由多个三态门组成，用来驱动地址总线和控制总线。,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtri_buf8ISPORT(din:INSTD_LOGIC_VECTOR(7DOWNTO0);dout:OUTSTD_LOGIC_VECTOR(7DOWNTO0);en:INSTD_LOGIC);ENDtri_buf8;ARCHITECTUREaOFtri_buf8ISBEGINPROCESS(din,en)BEGINIF(en=1)THENdout=din;ELSEdout=ZZZZZZZZ;ENDIF;ENDPROCESS;ENDa;,3.双向总线缓冲器用于对数据总线的驱动和缓冲。,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtri_bigateISPORT(a,b:INOUTSTD_LOGIC_VECTOR(7DOWNTO0);en:INSTD_LOGIC;dr:INSTD_LOGIC);ENDtri_bigate;ARCHITECTUREaOFtri_bigateISSIGNALaout,bout:STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(a,en,dr)BEGINIF(en=0ANDdr=1)THENbout=a;ELSEbout=ZZZZZZZZ;ENDIF;b=bout;ENDPROCESS;PROCESS(b,en,dr)BEGINIF(en=0ANDdr=0)THENaout=b;ELSEaout=“ZZZZZZZZ”;ENDIF;a=aout;ENDPROCESS;ENDa;,6.2时序逻辑电路设计,时序逻辑电路概念：如果电路在某一时刻的输出状态不仅取决于电路在这一时刻的输入状态，而且与电路过去的状态有关，也就是说电路具有了记忆功能，这种电路就叫作时序逻辑电路。时序逻辑电路中能够完成记忆功能的电路叫做触发器，它是最重要、最基本的时序单元电路。,6.2.1时钟信号与复位信号,1.时钟信号：时序电路都以时钟信号为驱动信号，时序电路只是在时钟信号的边沿到来时，其状态才发生改变，因此时序电路通常以时钟进程形式来描述时序电路的执行条件。时钟边沿的描述信号：上升沿ifclk=1andclklast_value=0andclkeventthen下降沿ifclk=0andclklast_value=1andclkeventthen,2.触发器的同步与非同步复位：同步复位：当复位信号有效且给定的时钟边沿到来时，触发器才被复位。非同步复位：一旦复位信号有效，触发器就被复位。,触发器的同步复位同步复位：首先在进程的敏感信号中只有时钟信号且用if语句描述必要的复位条件。,触发器的非同步复位非同步复位又称异步复位：首先在进程的敏感信号中除时钟信号以外，还应加上复位信号；其次是用IF语句描述复位条件；最后在ELSIf段描述时钟信号边沿的条件，并加上EVENT属性。,6.2.2触发器,1.D锁存器,6.2.2触发器,1.D锁存器,2.非同步复位D锁存器,非同步夏位的D锁存器和一般的D锁存器的区别是多了一个复位输入端clr。当clr0时，其q端输出被强迫置为“0”。clr又称清零输入端,IF(clr=0)THENq=0;ELSIF(clkEVENTANDclk=1THEN)q=d;ENDIF;ENDPROCESS;ENDrt1;,3.非同步复位/置位D锁存器,非同步复位/置位D锁存器的电路符号如图7-19所示，clr和pset位为复位、置位端。当clr0时复位，使q0；当pset0时置位，使q1。,4.JK触发器带有复位/置位功能的JK触发器的电路符号及真值表如图所示：,6.2.3比较复杂的寄存器,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYshiftISPORT(a,clk:INSTD_LOGIC;b:OUTSTD_LOGIC);ENDshift;ARCHITECTUREBEHAVOFshiftISCOMPONENTdffPORT(d,clk:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALz:STD_LOGIC_VECTOR(0TO8);BEGINz(0)=a;g1:FORiIN0TO7GENERATEdffx:dffPORTMAP(z(i),clk,z(i+1);ENDGENERATE;b=z(8);ENDBEHAV;,2.循环移位寄存器,LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;PACKAGEcpacISPROCEDUREshift(din,s:INSTD_LOGIC_VECTOR;SIGNALdout:OUTSTD_LOGIC_VECTOR);ENDcpac;PACKAGEBODYcpacISPROCEDUREshift(din,s:INSTD_LOGIC_VECTOR;SIGNALdout:OUTSTD_LOGIC_VECTOR);VARIABLEsc:INTEGERrange0to7;BEGINsc:=CONV_INTEGER(s);FORiINdinRANGELOOPIF(sc+i=dinLEFT)THENdout(sc+i)=din(i);ELSEdout(sc+i-1dinLEFT)=din(i);ENDIF;ENDLOOP;ENDshift;ENDcpac;,利用该移位过程描述8位循环左移的寄存器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;Usework.cpac.all;ENTITYbsrISPORT(din:inINSTD_LOGIC_vector(7downto0);s:instd_logic_vector(2downto0);clk,enb:inSTD_LOGICdout:outstd_logic_vector(7downto);ENDshift;,ARCHITECTURErtlOFbsrISBEGINprocess(clk)beginifclkeventandclk=1thenifenb=0thendout=din;elseshift(din,s,dout);endif;endif;endprocess;ENDBEHAV;,6.2.4计数器,1.同步计数器,(2)可逆计数器,(3)60进制计数器。,LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;ENTITYcout60_vISPORT(CLRN,LDN,EN,CLK:INSTD_LOGIC;Da:INSTD_LOGIC_VECTOR(3downto0);Db:INSTD_LOGIC_VECTOR(2downto0);Qa:OUTSTD_LOGIC_VECTOR(3downto0);Qb:OUTSTD_LOGIC_VECTOR(2downto0);RCO:OUTSTD_LOGIC);ENDcout60_v;ARCHITECTUREaOFcout60_vISBEGINPROCESS(Clk)VARIABLEtmpa:STD_LOGIC_VECTOR(3downto0);VARIABLEtmpb:STD_LOGIC_VECTOR(2downto0);BEGINIFCLRN=0THENtmpb:=000;tmpa:=0000;ELSEIF(ClkeventANDClk=1)THENIFLDN=0THENtmpa:=Da;tmpb:=Db;ELSIFEN=1THENIFtmpa=1001THENtmpa:=0000;IFtmpb=101THENtmpb:=000;ELSEtmpb:=tmpb+1;ENDIF;ELSEtmpa:=tmpa+1;ENDIF;ENDIF;ENDIF;ENDIF;Qa=tmpa;Qb=tmpb;RCO=tmpb(0)ANDtmpb(2)ANDt