这样就可以在fpga内部实现2个双口ram了VIP

1、这样就可以在 fpga内部实现 2 个双口 ram了这样就可以在fpga内部实现2 个双口ram了经过斑竹的提示，修改了程序，现在就可以在fpga内部实现2 个双口ram了，可以实现乒乓操作了library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_ARITH.all;use IEEE.STD_LOGIC_UNSIGNED.all;entity dualportram isport(clk : instd_logic;-dout_1: inout std_logic_vector(7 downto 0);-dout_2: inout

2、 std_logic_vector(7 downto 0)dout : inout std_logic_vector(7 downto 0);end dualportram;architecture action of dualportram iscomponent lpmramdp_1PORT(data: IN STD_LOGIC_VECTOR (15 DOWNTO 0);wren: IN STD_LOGIC := 1;wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);rdaddress : IN STD_LOGIC_VECTOR (12 DOWNT

3、O 0);clock: IN STD_LOGIC;q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);end component;component lpmramdpplusPORT(datawrenwraddressrdaddressclock: IN STD_LOGIC_VECTOR (15 DOWNTO 0);: IN STD_LOGIC := 1;: IN STD_LOGIC_VECTOR (12 DOWNTO 0);: IN STD_LOGIC_VECTOR (13 DOWNTO 0);: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTO

4、R (7 DOWNTO 0);end component;signal wrCount_1 : std_logic_vector (11 DOWNTO 0);signal rdCount_1 : std_logic_vector (12 DOWNTO 0);signal dataIn_1 : std_logic_vector (15 downto 0);signal dataOut_1 : std_logic_vector (7 downto 0);signal wrCount_2 : std_logic_vector (12 DOWNTO 0);signal rdCount_2 : std_

5、logic_vector (13 DOWNTO 0);signal dataIn_2 : std_logic_vector (15 downto 0);signal dataOut_2 : std_logic_vector (7 downto 0);signal flag:std_logic;beginprocess(clk)beginif rising_edge(clk) thenwrCount_1 = wrCount_1 + 1;rdCount_1 = rdCount_1 + 1;wrCount_2 = wrCount_2 + 1;rdCount_2 = rdCount_2 + 1;flag = not flag;if (flag = 1) thendout = dataOut_1;elsedout dataIn_1,wren= 1,wraddress= wrCount_1,rdaddress= rdCount_1,clock= clk,-q= dout_1q= dataOut_1);u2: lpmramdpplusPORT map(data= dataIn_2,w