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1、IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 20111881A 550- W 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error CorrectionSang-Hyun Cho, Student Member, IEEE, Chang-Kyo Lee, Student Member, IEEE, Jong-Kee Kwon, Member, IEEE, and Seung-Tak Ryu, Member, IEEEAbstractA spee

2、d-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible hardware overhead. The redundant decision cycles between

3、stages reconfigure the capacitor connection of the DAC. These redundancies guarantee 10-b linearity under 4-b-accurate DAC settling in the MSB decision and the optimally designed ADC enhances the conversion speed by 37%. A prototype ADC was implemented in a CMOS 0.13- m technology. The chip consumes

4、 550 W and achieves a 50.6-dB SNDR at 40 MS/s under a 1.2-V supply. The figure-of-merit (FOM) is 50 fJ/conversion-step.Index TermsAddition-only digital error correction (ADEC), asynchronous, digital error correction, multistep binary error cor- rection, SAR ADC.Fig. 1. Number of published papers on

5、SAR ADC.I. INTRODUCTIONRAPID expansion of interestAR ADCs is reflected inthe number of related papers that have appeared in re-and thereby lower the power consumption. Capacitor mismatch calibration could further reduce the total capacitance by relaxing the matching-limited capacitor size requiremen

6、t 3. Recently, several smart DAC switching techniques have also mitigated wasted power consumption 4, 5.While the low-power characteristic of SAR ADCs is very at- tractive, the large number of decision cycles for a single conver- sion is a fundamental drawback for high-speed operation. Re- cently, h

7、owever, not only advanced process technology but also many smart circuit techniques have accelerated the conversion speed. Digital error correction using decision redundancy in- creases the speed of the DAC operation. Other various architec- tures employing multiple ADCs in parallel (time-interleavi

8、ng orcent major circuit conferences, as Fig. 1 illustrates. A total of 53 SAR ADCs were reported in the IEEEs five major circuit con- ferences (ISSCC, VLSI Symposium, CICC, ASSCC, and ESS- CIRC) from 2002 to 2010. While there were relatively few pub- lications up to 2005, the number of published pap

9、ers has grown rapidly since 2006, and a whole session was designated for SAR ADC in ISSCC 2010.consumption. In principle, SAR ADCs can be designed with no static power consumption. Many previous works have tried to further reduce the power consumption, as the operating power consumption can be consi

10、derable in certain applications due to high speed internal switching and large capacitor driving. Tra- ditionally, a segmented capacitor DAC structure 1, 2 can re- duce the total capacitance as long as kT/C noise is not limited,multibit/cycle) oreries (hybrid or multistage) 612 alsoenhance the conve

11、rsion speed.Owing to the various advances discussed above, SAR ADCsnow cover a very wide range of applications, as Fig. 2 shows. Effective number of bits (ENOB) of the 53 papers in Fig. 1 areManuscript received December 01, 2010; revised February 05, 2011;accepted March 28, 2011. Date of publication

12、 June 09, 2011; date of current version July 22, 2011. This work was supported in part by the National Research Foundation of Korea funded by the Korean government (MEST) under Grant NRF-2010-0001546 and by the IT R&D program of the Ministry of Knowledge Economy, Republic of Korea, under Grant 2008-

13、S-015-01. This paper was approved by Guest Editor Pavan Kumar Hanumolu.S.-H. Cho, C.-K. Lee, and S.-T. Ryu are with the Department of Electricalplotted according to their sampling rate. They can be catego- rized into four groups. Group-A with low conversion frequen- cies can be applicable to sensor

14、networks and biomedical appli- cations. Group-B is suitable for video and many general purpose applications, and their performances are comparable to those of pipelined ADCs. Group-C can be used for UWB, SERDES, and disk drive read channels, which usually utilized flash ADCs. Fi- nally, SAR ADCs in

15、group-D are used for high-speed optical communications with massive time-interleaving.Among them, the SAR ADCs in group-B have shown supe- rior power efficiencies relative to pipelined ADCs with similar resolutions and speeds. In order to compare the performances,Engineering, Korea Advancedtitute of

16、 Science and Technology (KAIST),Daejeon 305-732, Korea (e-mail: stigmakaist.ac.kr; ck_leekaist.ac.kr; stryuee.kaist.ac.kr).J.-K. Kwon is with the Electronics and Telecommunications Research tute, Daejeon, 305-700, Korea (e-mail: jkkwonetri.re.kr).ti-Color versions of one or more of the figures in th

17、is paper are available onlineat .Digital Object Identifier 10.1109/JSSC.2011.21514500018-9200/$26.00 2011 IEEE1882IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 2011Fig. 2. ENOBs versus sampling rate of SAR ADCs from recent major conferences.Fig. 3. FOM compari

18、son: SAR ADCs versus pipelined ADCs.Fig. 4. Standard binary decision SAR ADC. (a) Simplified block diagram of a SAR ADC. (b) SAR operations under the ideal DAC settling condition. (c) 4-b standard binary SAR ADC.14 recent pipelined ADCs having similar resolutions and con- version speeds to those of

19、SAR ADCs were selected (8 b12 bresolution and 20200 MS/s conversion speed) and their fig-ures-of-merit (FOMs) were plotted with those of SAR ADCs in Fig. 3. The FOM formula used isuses digital addition only, as in 14. In addition, the prototype realizes low power consumption as well via an energy-ef

20、ficient DAC switching.(1)This paper is organized as follows.ection II, the deci-sion algorithms in a standard binary SAR ADC and represen-whereis the sampling frequency andis the effectivetative redundancy-aided SAR ADCs are reviewed. Section III introduces several key concepts in the proposed desig

21、n such as straightforward DAC switching and the addition-only digital error correction (ADEC). Section IV discusses the optimized usage of the proposed ADEC algorithm and presents the de-resolution bandwidth. Unlike the pipelined ADCs whose FOMsare widely distributed, most of the SAR ADCs show an FO

22、M of less than 100 fJ/conversion-step. This figure demonstrates the excellent power efficiency of SAR ADCs in group-B.The authors have been interested in replacing pipelined ADCs in group-B with SAR ADCs by establishing a well-de- fined speed enhancing conversion technique. This paper introduces a s

23、ystematic digital error correction (DEC) tech- nique for high speed DAC operation in a binary decision SAR ADC by extending the concept in 13. While multistage based structures such as pipelined ADCs have well established digital error correction techniques to relax the decision errors in MSBs 14, s

24、imilar techniques for SAR ADCs introduced thus far are less systematic or require hardware overhead. The DEC technique in this paper leaves the capacitor DAC intact andtailed implementation of the 10-b prototype ADC. the measurement results are discussed.ection V,II. REVIEW OF CONVENTIONAL SA ALGORI

25、THMSFig. 4(a) shows a generalized block diagram of an SAR ADC. It is composed of sample-and-holder (S/H), DAC, comparator, and successive approximation (SA) control logic.Fig. 4(b) shows a sampled signaland a DAC wave- settles to 1/2formin every decision. First,for the MSB decision, and the comparat

26、or generates, since the input is lower than 1/2. Thus, theCHO et al.: 550- W 1-b 40-MS/s SAR ADC WITH MULTISTEP ADEC1883Fig. 5. (a) Erroneous SA operation due to incomplete DAC settling. (b) Nonbinary redundant SA. (c) Binary redundant SA.first determined input rangeis the lower half of thefullnonbi

27、nary SAR ADC compensates the settling error. It adds a fixed percentage of redundancy to DIR for every decision by considering the possible settling error (in this example, how- ever, the redundancy ratio could not be fully illustrated due to limited resolution). The redundancy amount and the correc

28、ted binary output code can be calculated by the digital circuitry such as the arithmetical unit and ROM, as in 15. This gives an op- portunity to fix the previous decision error and allows the DAC to settle inaccurately within the amount of redundancy. A sub- radix-2 weighted DAC 3 could implement d

29、igital error correc- tion without complicated logic in the DAC control. However, the layout of the nonbinary capacitor array may not be trivial and usually the scheme requires digital calibration for linearity com- pensation. Fig. 5(c) shows a binary-decision-based redundancyscale. The DIR in each d

30、ecision phase is illustrated graphicallyby the gray bar. The next decision threshold, i.e., the (MSB-1) bit is placed at the center of, for, as shown. Byinphase, and achieves the next bit,following the same principle, finally, the correct conversionresult ofis achieved. This repeated decisionsequenc

31、e generalizes the binary SA operation: It sequentiallydecides bits from MSB to LSB by successively dividing the previous DIRs.Typically, since switched-capacitor circuits can perform a signal sampling function, the S/H and DAC are often merged in a switched-capacitor array, as Fig. 4(c) shows. The D

32、AC shown here is in its MSB-2 bit decision phase in Fig. 4(b). The connections of the two largest capacitors (8C and 4C) are already fixed by the preceding decisions, and 2C is now in use for the next decision threshold. Thus, we may refer to the former and the latter capacitors as fixed elements (F

33、E) and variable elements (VE), respectively. Note that, although the sample-and-hold (S/H) function is embedded in the DAC, wealgorithm 16.tead of adding redundancy to every decisionphase, the technique adds it to specific decision phase(s), such asin Fig. 5(c), whose size is half of the previous DI

34、R,.Thus, the range ofhas the same size as that of the pre-ceding phase. Contrary to the nonbinary SA, recent binary SAR ADCs with redundancy 16, 17 considerably reduce the hard- ware overhead.Nevertheless, previous approaches, including the use of ad- ditional capacitors required for redundancy 16,

35、a burdensome binary-to-thermometer decoder in the control circuit 15, still have room for further improvement. The proposed ADEC method, first reported in 13, does not require additional capacitors for the DAC or complicated logic in the decision loop. The only necessary components are simple logic

36、gates for digital addition. This paper presents a speed optimized SAR ADC with the ADEC algorithm and a low power DAC switching method.can simply separatefrom, becauseis describedasas in the function shown in Fig. 4(a).Fig. 5(a) shows what happens when DAC settling is incom-plete. At slow, the wrong

37、 MSB settling. Therefore,is achieved due to is determined erroneouslyto be the upper half of the full scale. Since the conventional bi-nary decision is an irrevocable process, the followingdi-vides the tually theregardless of whether it is correct, and even-becomes “1000” while its correct value is0

38、110. This implies that the DAC settling in every decision mustbe accurate enough within a 1 LSB error, and this limits the SA A/D conversion speed 15.Such a tight requirement for DAC settling in a standard binary SAR ADC can be relaxed by allowing some decision redundan- cies. Fig. 5(b) and (c) illu

39、strate two representative methods: non- binary redundancy and binary redundancy. Fig. 5(b) shows howIII. STRAIGHTFORWARD DAC SWITCHING AND ADEC SA ALGORITHMHere, the operational principle of ADEC SA is discussed with a simple example of a 4-b ADC. Before we discuss this in detail,1884IEEE JOURNAL OF

40、 SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 2011Fig. 6.Comparison of the conventional and straightforward DAC switching at (a) MSB decision phase and (b) MSB-1 decision phase.some background of this work is discussedections III-Anot been used yet, no switch-back operation is required, unlike in th

41、e conventional design refer to the dotted linedin Fig. 6(b). All of the remaining decisions follow the same switching fashion, proceeding to smaller capacitors: fromand III-B: straightforward DAC switching and ADEC in a mul- tistage architecture.A. Straightforward DAC SwitchingConsiderable power con

42、sumption in a conventional SAR ADC may occur due to capacitor DAC switching 5. In order to reduce the wasted power, this work introduces a straightforward DAC switching method (note that the same concept has been studied by several groups independently 18, 19).to either 0 or. Note thatdoes not need

43、to beexactlyat the center of the full reference range in a fully differentialcircuit, because it is a common level and will be cancelled out. Similar operational principles to the straightforward decision are also found in earlier designs, although their DAC struc- tures and/or control methods are s

44、lightly different 4, 20, 21. Compared with these approaches, the bottom-plate sampling- based straightforward operation in this design can provide better linearity, in principle, and thus it is suitable for higher resolu- tions 38. It is worth noting that the straightforward decision method reduces

45、the number of capacitors by half. By elimi- nating the switchback operations and by reducing the capac- itor size (as long as the design is not limited by kT/C noise) and reducing the charging step by half, the straightforward SA switching consumes very little power, as a recent study has cal-culate

46、d 18.Fig. 6 explathe differences between the conventionaland the straightforward DAC switching scheme using a 4-b SAR ADC. Since the MSB notifies whether the input is largeror smaller than half of the full scale, the MSB can be deter- mined by placing the sampled input at the comparator and bycompar

47、ing it withswitching top right of Fig. 6(a)in the straightforward tead of generating 1/2using the capacitor DAC bottom right of Fig. 6(a).For the next bit decision, since the input is located below 1/2, the propercan be generated byconnecting 4C to “0” while the other capacitors remain atB. ADEC SA

48、AlgorithmFig. 7 shows the operational principle of the ADEC in a two- step ADC. By shifting up all of the decision thresholds of theFig. 6(b). The straightforward DAC switching produces a proper reference level without the largest capacitor, (8C), owingto the additionalreference. In addition, since

49、the DAC hasCHO et al.: 550- W 1-b 40-MS/s SAR ADC WITH MULTISTEP ADEC1885Fig. 7. Review of ADEC in a two-step ADC.Fig. 8. Analogy of a two-step ADC and a SAR ADC.coarse ADC by 1/2 LSB of its own resolution, the subtraction operation can be eliminated from the error correction. The same concept can b

50、e applied for a SAR ADC with redundant decision110 with an ideal fine flash ADC, and finally the error-corrected full code 0110 is achieved by adding MSBs and LSBs with 1-b overlap. On the other hand, the redundancy in the SAR ADC isphase(s), similar to the methods discussedection II-B. Fig. 8implem

51、ented byerting an additional decision step,. Theshows an analogy of ADEC algorithms in a two-step ADC and the SAR ADC in 22 using a 4-b example. DAC settling errorsdesired fine conversion range is determined by the MSBs (00),and the fine conversion starts atby placing the DAC levelduring the decisio

52、n phases for MSBs in the SAR ADC can be corrected by the ADEC algorithm, as can the comparator errors in a two-step ADC, because they have identical decision thresh- olds. As with the two-step ADC, the decision procedure in the SAR ADC is virtually divided into two steps of 2-b-coarse and 3b-fine wi

53、th 1-b redundancy (2-3-b configuration). Both ADCsat the center of. Two more bit decisions aftertheredundant decision produce a total of 3-b LSBs. Accordingly,since the MSBs and LSBs from the SAR ADC are identical to those from the two-step ADC, the code error occurred during the coarse SA conversio

54、n can be eliminated by addition only as long as the error amount is less than 0.5 LSB of the coarse res- olution. This relaxes the DAC settling requirement and we can speed up the SA operation even with an increased number of conversion cycles.have coarse decision thresholds at 3/8 and 5/8, which de

55、-viate from those of an ideal flash ADC by 0.5 LSB of coarseresolution. In a SAR ADC, this threshold shift canbe realized by starting the MSB decision with the DAC levelThe required minimum DAC settling timefor the MSBat 5/8, rather than at 1/2. In the example,decision in a conventional SA algorithm

56、 can be found bythe two-step ADC has comparator position error (black triangle)and, similarly, the SAR ADC has slowsettling, which(2)both result in decision error. For the given input, bothADCs generate incorrect MSBs of 00. In the following fine con- version process, the two-step ADC extends its re

57、ference rangewhereis the maximum time constant of the DACsettling and is the entire resolution of the ADC. For a 10-b example, if we assume a constant DAC settling time for every decision phase,to the upper and lower sides by 0.5 LSBs of the coarse conver- sion resolution. The fine ADC then determin

58、es the 3b LSBs ofthe total DAC settling time needed is(and).1886IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 2011DAC settling condition, andis decided as the gray barindicates in ub-. The first DAC operation then connects the 4C to 0 to determine the next bit. Then,is obtained andis determined as shown in,