若控制误差过大.

1、 i.e. , s 1 Problem 1. Simply answer the following questions. (a) Numerical approximati ons of in tegrati on(Ch.8 p.8p.15) 1 仃 n 0 1s n s 1 1s1 ill n nS Let D s Hence, D z D 1. Left-side rule: s 2. Right-side rule: s z 1 1 z 1 T 3. Trapezoidal rule: 31 z 2 T 1 4z 1 z 2 5. Step Inv aria nee. (p.15)/

2、Impulse Inv aria nee. (p.13)/ Ramp Inv aria nee. (p.43) 6. Matched z-tra nsform. (p.26) 4. Simps ons rule: s 補充 Numerical approximations of differentiation 1 z 1 (1) Backward differe nee: s T z 1 (2) Forward differe nee: s T |z eTs eTs (Ch.8 p.54p.55) 若控制誤差過大，經過積分器放大後造成致動器輸出爬升至上限，造成控制 輸出無法繼續提升系統輸出，達

3、到積分飽和。此時迴路視同斷路，積分器變成不 (b) Anti Win dup Schemes of Digital PID control 穩定的裝置，且系統存在迴授路徑因過載而燒掉的危險性。 當發生積分飽和時，除非重新給予積分器一個正常的數值以清除累積的積分 效應，不然會持續輸出一個極大值。 Anti Windup系統架構如右： (或參考上方圖片) If each in tegrator s 1 can be replaced by its digital equivale nt, 1 s (c) Design methods to synthesize digital controller

4、s: 1. Frequency Response Method 2. Root-Locus Method 3. State-Space Method 4. Polynomial Approach (d) Controllability & Observability Controllability: x k 1 Ax k Bu k is controllable if there exists a sequence of input u(0), u(1), u(2), ,u(n-1) that can tran slate the system from any in itial state

5、x(0) to any final state x(N) with N finite. Observability: x k 1 Ax k Bu k is observable if for any initial state x(0), it can be y k Cx k Du k calculated from the N measureme nts y(0), y(1),y(N-1) with in put u(0), u(1), u(N-1), with N finite. (e) Digital Controllers: (Ch.13 p.35p.38) IPC-based con

6、trollers: 優點： 1. 已經考慮了溫度、灰塵、水、震動與 EMI 等問題 2. 較一般 PC 更小巧 3. 耐惡劣環境，壽命大於三年 4. 直接記憶存取，記憶體容量大 5. 作業系統支援普及 (如 DOS, Windows, CWIN 等)，發展軟體支援多樣化 6. 擁有一般 PC 之功能，如具高速數據處理能力，發展工具多元化，有現成多 樣的擴充介面，如數位介面卡、 A/D 卡與 D/A 卡，強大的網路功能，高開放 性的架構，具親和力與方便操作的人機介面以及價格競爭力高等 7. 生產廠商較多，具模組化設計，有較統一的產品規格 8. 維修容易 缺點： 1. 成本高昂，較不適合用於大量低

7、價的商品 2. 體積較大，不適合用於小型系統 DSP-Based Controllers: 優點： 1. 採用RISC運算架構，處理速度可快達101600 MIPS以上 2. 乘法運算透過專用硬體處理，運算速度快，可縮短複雜算術運算的控制法則 與數位訊號處理的執行時間 3. 具有定點與浮點運算功能 4. 晶片內涵 RAM、ROM、Serial I/O、CAM bus、A/D、PWM、Flash memory 等周邊元件，產品可靠度高，電路設計簡單 5. 體積小，耗電量小，價格便宜，易於商品化與工業產品化 6. 具有多處理器平行處理能力 缺點： 1. 發展與作業系統受侷限，大多受限於 C/C+或

8、ASM語言 2. 資料儲存量較小，記憶容量有限 3. 人機介面較不易處理 4. 硬體實現較PC-based控制器困難，無泛用形式，修改變更彈性不高 5. 軟體支援較PC-based控制器少，甚至必須自行完成 Microcontroller-Based Controllers: 優點： 1. 價格低廉，適合小型控制器產品，如家電、 3C 產品等 2. 體積小，甚至有 SMT/SMD 形式，適合消費性產品 3. 內涵 RAM 、ROM、Serial I/O 等周邊元件，產品可靠度高，電路設計簡單 4. 耗電量少，甚至有省電裝置，可用於電池供電之攜帶型產品系統 缺點： 1. 運算速度不及IPC-Ba

9、sed與DSP-Based控制器 2. 發展工具侷限於C/C+及ASM語言 3. 人機介面不易處理 4. 硬體實現後，修改彈性不高 5. 僅有整數運算或定點小數運算功能 (f) Implementation issues of digital controllers: (Ch.13 p.3) 1. Selection of sampling rate. 2. Interfacing to sensors: prefilter selection, computational delay. 3. Choice of A/D and D/A converters. 4. Interfacing t

10、o nonlinear actuators. 5. Interfacing to human operators. 6. Numerical errors and digital controller structures. 7. Word length selection in digital arithmetic device and memory. 8. Selection of digital computation devices. 9. Programmi ng: real-time program ming software engineering in digital cont

11、rol systems. (g)雙自由度補償/控制器之四大結構圖(Ch. 8 p.13p.14) (Two degree-of-freedom compe nsati on) 1. 串聯迴授補償(Series-feedback compensation) 2.前饋補償器 (Forward / Feed-forward compensation) 匚 3.命令式前饋控制器(Comma nd-feed-forward compe nsati on) 4.前饋負載干擾 (Forward-load disturbanee with series compensation) + RjG* (h) In

12、terfac ing tech nique to non li near actuator.(Ch.13 p.16) 1. All the con trol algorithms are desig ned based-on lin ear models of the pla nt. 2. Non li near effects of physical actuators must be take n into acco unt for the control system, especially duri ng startup and shutdow n, as well as large

13、cha nges. 3. One of non li near effects caused by non li near actuators is in tegrator win dup. 4. Here simple heuristic methods are used to deal with non li near actuators. (i) Phase-lag compe nsator desig n procedure. (Ch.9 p.20p.21) (Us ing freque ncy resp onse method) 1. Determine the frequency

14、w1, at which the phase angle G j w is approximately180m 5o . The phase margin of the compensated system will occur at approximately the freque ncy. 2. Choose w0 0.1 w1 to ensure that little phase lag is introduced at 皿.Actually, the compensator will introduce approximately 5o phase lag, which has be

15、en acco un ted for in step 1. 3. At 期，we want D j G j 1. Since the gain of the compensator at high freque ncies is a0 wp. wo(where ao is the compe nsator DC gai n), the n a0 wp G j w1 wo 1a0 wp wo 1 G j w1 Solving the last two equatio ns for wp yields wp 0.1 w1 the desig n is a。G j w1 now complete,

16、since the compe nsator DC gain, pole, and zero are known. (j) Equivale nt discrete-time con troller Si nee Ax Bu t y Cx and u t Mr t Lx t Ax B r Lx A BL x Br The approxiamtely discrete -time controller is u kT r kT x kT where T A BL - T LB M Problem 2. True-False Problem (a) T (b) T (e) F (d) T (e)

17、T (f) F (g) T (h) F (i) T (j) F U s 0, K 0, Ti0, Td0 a Derivative /Differential 2 z 1 Si nee s T z 1 1T z1T q1-i -i Letwhere q z , q z s2 z12 q1 1. P k Kbr k Ky k t 1 K 1 2.1 s R s Y s Ti s I k e k K1e s Ti s 4 I 3. D s q 1 5s、， 1Tds 1芒 Kbi q 1 e where b d T z 1 2KTd z 1 N 2 z 1 2KTd q 2Td 2Td 2Td N

18、 Let z Problem 3. Controller Realization 2KTd q 1 2Td NT 2Td NT 2Td N NT 2NTd Kbd q 2Td NT q 2Td “ NT d 2Td NT 2Td NT 2NTd 2Td T 亓 NT and bd b u k P k Ik D k Kbi q 1 Kbd q 1 Kbr k Ky k -e k Y k q 1 q d q 1 q d U k Kb q 1 q d r k K q 1 q d y k Kbi q 1 q d r k Kbi q 1 q d y k Kbd q i 1 2 y k R q u kT

19、T q r kT S q y kT R q q 1 q d 2 q 1 d q d where T q Kbq2 K b 1 b d b q K d b bi S q K 1 bd q2 K 1 d b i 2bd q K d i： )i dbd d Problem 4. Dead-beat Control Design (HW12 p.1) Since 10 z 0.510z 5 z2 0.9z 0.18 z2 0.9z 0.18 K z 乙Kz a z piz P1 The unit step dead beat control design 1 D z G z T z z 1 D z G

20、 z D10z 5 1 z z2 0.9z 0.18D z 10 z 0.5 z10z 5z 0.3 z 0.6 D z 10 z 0.5 1 D z z2 0.9z 0.18 10D z z z 0.5 z 0.3 z 0.6 D z 10 z 0.5 10D z z 1 z 0.5 z 0.3 z 0.6 z 0.3 z 0.6 10 z 1 z 0.5 另解 G z D z 不正確，但有部份給分 10 z 0.510Z 5 z2 0.9z 0.18 z2 0.9z 0.18 K z 乙Kz a z Pi z p! The unit step dead beat control desig

21、n 1 D z G z T z z 1 D z G z 2 1zp1z 0.9z 0.18 Kz a 10z 5 z 1 Kz a 10z 5 z p1 z2 0.9z 0.18 Kz a Kz Kz,10z 5 z Pj z 0.9z 0.18 10z 5 10Kz2 5K 10Kz1 z 5Kz1 z30.9z20.18z p1z20.9p1z0.17p1 10Kz2_5K10 z2 5Kz1 10Kz25K 10KZ1 z 5KZ1 z30.95 10K z20.180.9p1 5K 10a z 0.18 5K 10K1 K 0.1 5K 10Kw 0.9 p1 10K 5Kz1 0.1

22、8 0.9p1 5K 10a 0.18p) 5a 0 0.5 zj 0.9 p1 1 0.5乙 0.18 0.9 p) 0.5 zj N0.36p1 zi p10.4 0.5乙 0.9p10.68 no solution z10.36p1 zP1 D z無法求得(題目設計問題) Problem 5. Model Matchi ng Con troller Desig n (HW13 p.2) Y z 0.4z 0.2 0.4z 0.2 B z bz b1 U z z 1 z 0.4 2 z 1 1.4z 0.4 A z 2 z aza? a2 0 bi 0 0.4 0 0.2 0 E 印 a2 b bi 1.4 0.4 0.4 0.2 1 a1 0 b 1 1.4 0 0.4 0 1 0 0 0 1 0 0 and D z c z 0 z B z H1 z z 0.4z 0.2 z 0.5 z 0 0.1z 0.4z2 0.4z 3 0 0.1 0.4 T 0.4 1D T M E 0.2 0.4 0.4 1.9 1 0 1 0 T z z 1 0.4z 0.2 z z 1 1.9z 0.4 System control law : z U z Gmodel H 1 z 0 z R z z Y : z U