ARM学习经验 UART串口无法正确输出字符

1、 UART串口无法正确输出字符 使用.s文件进行初始化设置，程序代码如下： ; Standard definitions of Mode bits and Interrupt (I when I bit is set, IRQ is disabled F_Bit EQU 0 x40 ; when F bit is set, FIQ is disabled UND_Stack_Size EQU 0 x00000000 SVC_Stack_Size EQU 0 x00000080 ABT_Stack_Size EQU 0 x00000000 FIQ_Stack_Size EQU 0 x000000

2、00 IRQ_Stack_Size EQU 0 x00000100 USR_Stack_Size EQU 0 x00000400 ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE USR_Stack_Size _initial_sp SPACE ISR_Stack_Size Stack_Top Heap_Size EQU 0 x0

3、0000000 AREA HEAP, NOINIT, READWRITE, ALIGN=3 _heap_base Heap_Mem SPACE Heap_Size _heap_limit ; System Control Unit (SCU) definitions SCU_BASE EQU 0 x5C002000 ; SCU Base Address (non-buffered) SCU_CLKCNTR_OFS EQU 0 x00 ; Clock Control register Offset SCU_PLLCONF_OFS EQU 0 x04 ; PLL Configuration reg

4、ister Offset SCU_SYSSTAT_OFS EQU 0 x08 ; System Status Register Offset SCU_PCGR0_OFS EQU 0 x14 ; Peripheral Clock Gating Register 0 Offset SCU_PCGR1_OFS EQU 0 x18 ; Peripheral Clock Gating Register 1 Offset SCU_PRR0_OFS EQU 0 x1C ; Peripheral Reset Register 0 Offset SCU_PRR1_OFS EQU 0 x20 ; Peripher

5、al Reset Register 1 Offset SCU_SCR0_OFS EQU 0 x34 ; System Configuration Register 0 Offset SCU_PECGR0_OFS EQU 0 x2C SCU_PECGR1_OFS EQU 0 x30 SCU_GPIOOUT0_OFS EQU 0 x44 SCU_GPIOOUT1_OFS EQU 0 x48 SCU_GPIOOUT2_OFS EQU 0 x4C SCU_GPIOOUT3_OFS EQU 0 x50 SCU_GPIOOUT4_OFS EQU 0 x54 SCU_GPIOOUT5_OFS EQU 0 x

6、58 SCU_GPIOOUT6_OFS EQU 0 x5C SCU_GPIOOUT7_OFS EQU 0 x60 SCU_GPIOIN0_OFS EQU 0 x64 SCU_GPIOIN1_OFS EQU 0 x68 SCU_GPIOIN2_OFS EQU 0 x6C SCU_GPIOIN3_OFS EQU 0 x70 SCU_GPIOIN4_OFS EQU 0 x74 SCU_GPIOIN5_OFS EQU 0 x78 SCU_GPIOIN6_OFS EQU 0 x7C SCU_GPIOIN7_OFS EQU 0 x80 SCU_GPIOTYPE0_OFS EQU 0 x84 SCU_GPI

7、OTYPE1_OFS EQU 0 x88 SCU_GPIOTYPE2_OFS EQU 0 x8C SCU_GPIOTYPE3_OFS EQU 0 x90 SCU_GPIOTYPE4_OFS EQU 0 x94 SCU_GPIOTYPE5_OFS EQU 0 x98 SCU_GPIOTYPE6_OFS EQU 0 x9C SCU_GPIOTYPE7_OFS EQU 0 xA0 SCU_GPIOTYPE8_OFS EQU 0 xA4 SCU_GPIOTYPE9_OFS EQU 0 xA8 SCU_GPIOEMI_OFS EQU 0 xAC SCU_WKUPSEL_OFS EQU 0 xB0 SCU

8、_GPIOANA_OFS EQU 0 xBC GPIO3_BASE EQU 0 x58009000 GPIO_DIR_OFS EQU 0 x400 GPIO_SEL_OFS EQU 0 x420 UART0_BASE EQU 0 x5C004000 UART1_BASE EQU 0 x5C005000 UART_FR_OFS EQU 0 x18 UART_ILPR_OFS EQU 0 x20 UART_IBRD_OFS EQU 0 x24 UART_FBRD_OFS EQU 0 x28 UART_LCR_OFS EQU 0 x2C UART_CR_OFS EQU 0 x30 UART_IFLS

9、_OFS EQU 0 x34 UART_IMSC_OFS EQU 0 x38 UART_ICR_OFS EQU 0 x44 UART_DMACR_OFS EQU 0 x48 ; Constants SYSSTAT_LOCK EQU 0 x01 ; PLL Lock Status ; Flash Memory Interface (FMI) definitions (Flash banks sizes and addresses) FMI_BASE EQU 0 x54000000 ; FMI Base Address (non-buffered) FMI_BBSR_OFS EQU 0 x00 ;

10、 Boot Bank Size Register FMI_NBBSR_OFS EQU 0 x04 ; Non-boot Bank Size Register FMI_BBADR_OFS EQU 0 x0C ; Boot Bank Base Address Register FMI_NBBADR_OFS EQU 0 x10 ; Non-boot Bank Base Address Register FMI_CR_OFS EQU 0 x18 ; Control Register ; APB Bridge 1 APB Bridge 0 Buffered Base Address APB0_NBUF_

11、BASE EQU 0 x58000000 ; APB Bridge 0 Non-buffered Base Address APB1_BUF_BASE EQU 0 x4C000000 ; APB Bridge 1 Buffered Base Address APB1_NBUF_BASE EQU 0 x5C000000 ; APB Bridge 1 Non-buffered Base Address FMI_CR_Val EQU 0 x00000018 ;0 FMI_BBSR_Val EQU 0 x00000004 ;1 FMI_BBADR_Val EQU 0 x00000000 ;2 FMI_

12、NBBSR_Val EQU 0 x00000002 ;3 FMI_NBBADR_Val EQU 0 x00400000 ;4 FLASH_CFG_Val EQU 0 x00000000 ;5 STARTUP EQU 1 ;0 SCU_CLKCNTR_Val EQU 0 x00031404 ;1 SCU_PLLCONF_Val EQU 0 x000BC019 ;2 SCU_SYSSTATUS_Val EQU 0 x0000003F ;3 SCU_PWRMNG_Val EQU 0 x00000000 ;4 SCU_ITCMSK_Val EQU 0 x00000001 ;5 SCU_PCGR0_Va

13、l EQU 0 x000000FB ;6 SCU_PCGR1_Val EQU 0 x01FFCC39 ;7 SCU_PRR0_Val EQU 0 x00001873 ;8 SCU_PRR1_Val EQU 0 x00FEC839 ;9 SCU_MGR0_Val EQU 0 x00000000 ;10 SCU_MGR1_Val EQU 0 x00000000 ;11 SCU_PECGR0_Val EQU 0 x00000000 ;12 SCU_PECGR1_Val EQU 0 x00000000 ;13 SCU_SCR0_Val EQU 0 x000000B1 ;14 SCU_WKUPSEL_V

14、al EQU 0 x00000000 ;15 SCU_GPIOOUT0_Val EQU 0 x00000000 ;0 SCU_GPIOOUT1_Val EQU 0 x00000000 ;1 SCU_GPIOOUT2_Val EQU 0 x00000000 ;2 SCU_GPIOOUT3_Val EQU 0 x00000008 ;3 SCU_GPIOOUT4_Val EQU 0 x00000000 ;4 SCU_GPIOOUT5_Val EQU 0 x0000FFA8 ;5 SCU_GPIOOUT6_Val EQU 0 x00000000 ;6 SCU_GPIOOUT7_Val EQU 0 x0

15、000EAAA ;7 SCU_GPIOIN0_Val EQU 0 x00000000 ;8 SCU_GPIOIN1_Val EQU 0 x00000000 ;9 SCU_GPIOIN2_Val EQU 0 x00000000 ;10 SCU_GPIOIN3_Val EQU 0 x00000001 ;11 SCU_GPIOIN4_Val EQU 0 x00000000 ;12 SCU_GPIOIN5_Val EQU 0 x00000000 ;13 SCU_GPIOIN6_Val EQU 0 x00000000 ;14 SCU_GPIOIN7_Val EQU 0 x00000000 ;15 SCU

16、_GPIOTYPE0_Val EQU 0 x00000000 ;16 SCU_GPIOTYPE1_Val EQU 0 x00000000 ;17 SCU_GPIOTYPE2_Val EQU 0 x00000000 ;18 SCU_GPIOTYPE3_Val EQU 0 x00000000 ;19 SCU_GPIOTYPE4_Val EQU 0 x00000000 ;20 SCU_GPIOTYPE5_Val EQU 0 x00000000 ;21 SCU_GPIOTYPE6_Val EQU 0 x00000000 ;22 SCU_GPIOTYPE7_Val EQU 0 x00000000 ;23

17、 SCU_GPIOTYPE8_Val EQU 0 x00000000 ;24 SCU_GPIOTYPE9_Val EQU 0 x00000000 ;25 SCU_GPIOANA_Val EQU 0 x00000000 ;26 GPIO0_DIR_Val EQU 0X00 ;27 GPIO1_DIR_Val EQU 0X00 ;28 GPIO2_DIR_Val EQU 0X00 ;29 GPIO3_DIR_Val EQU 0X0A ;30 GPIO4_DIR_Val EQU 0X00 ;31 GPIO5_DIR_Val EQU 0X00 ;32 GPIO6_DIR_Val EQU 0X00 ;3

18、3 GPIO7_DIR_Val EQU 0X00 ;34 GPIO0_SEL_Val EQU 0X00 ;35 GPIO1_SEL_Val EQU 0X00 ;36 GPIO2_SEL_Val EQU 0X00 ;37 GPIO3_SEL_Val EQU 0X00 ;38 GPIO4_SEL_Val EQU 0X00 ;39 GPIO5_SEL_Val EQU 0X00 ;40 GPIO6_SEL_Val EQU 0X00 ;41 GPIO7_SEL_Val EQU 0X00 ;42 RTC_TR_Val EQU 0 x14100930 ;0 RTC_DTR_Val EQU 0 x201103

19、01 ;1 RTC_ATR_Val EQU 0 x00000000 ;2 RTC_CR_Val EQU 0 x00000000 ;3 RTC_MILR_Val EQU 0 x00000000 ;4 UART0_ILPR_Val EQU 0 x0034 ;0 UART0_IBRD_Val EQU 0 x004E ;1 UART0_FBRD_Val EQU 0 x0008 ;2 UART0_LCR_Val EQU 0 x0060 ;3 UART0_CR_Val EQU 0 x0301 ;4 UART0_IFLS_Val EQU 0 x0012 ;5 UART0_IMSC_Val EQU 0 x00

20、30 ;6 UART0_ICR_Val EQU 0 x0010 ;7 UART0_DMACR_Val EQU 0 x0000 ;8 UART1_ILPR_Val EQU 0 x0034 ;0 UART1_IBRD_Val EQU 0 x0138 ;1 UART1_FBRD_Val EQU 0 x0020 ;2 UART1_LCR_Val EQU 0 x0070 ;3 UART1_CR_Val EQU 0 x0301 ;4 UART1_IFLS_Val EQU 0 x0012 ;5 UART1_IMSC_Val EQU 0 x0010 ;6 UART1_ICR_Val EQU 0 x0010 ;

21、7 UART1_DMACR_Val EQU 0 x0000 ;8 UART2_ILPR_Val EQU 0 x000C ;0 UART2_IBRD_Val EQU 0 x004E ;1 UART2_FBRD_Val EQU 0 x0008 ;2 UART2_LCR_Val EQU 0 x0060 ;3 UART2_CR_Val EQU 0 x0301 ;4 UART2_IFLS_Val EQU 0 x0012 ;5 UART2_IMSC_Val EQU 0 x0030 ;6 UART2_ICR_Val EQU 0 x0010 ;7 UART2_DMACR_Val EQU 0 x0000 ;8

22、;/ System Ctrl ;/ Setup System Configuration (and SRAM Size) ;/ ;/ Setup Flash Memory Interface (FMI) ;/ ;/ Setup Clock ;/ ;/ Setup Peripheral Rese ;/ ;/ Setup Library Exception Handlers ;/ ;/ Setup Controller area network (CAN) ;/ ;/ Setup External Memory Interface(EMI) ;/ ;/ Setup Vectored interru

23、pt controller (VIC) ;/ ;/ Setup Universal asynchronous receiver transmitter (UART) ;/ ;/ Setup General purpose I/O ports (GPIO) ;/ ;/ Setup Real time clock (RTC) ;/ ;/ Setup 16-bit timer (TIM) ;/ ;/ SCR0_SETUP EQU 1 ;0 FMI_SETUP EQU 1 ;1 CLOCK_SETUP EQU 1 ;2 P_RESET_SETUP EQU 1 ;3 LEH_SETUP EQU 0 ;4

24、 CAN_SETUP EQU 0 ;5 EMI_SETUP EQU 0 ;6 VIC_SETUP EQU 0 ;7 UART_SETUP EQU 1 ;8 GPIO_SETUP EQU 1 ;9 RTC_SETUP EQU 0 ;10 TIM_SETUP EQU 0 ;11 ;T_Bit EQU 0 x20 PRESERVE8 ; Area Definition and Entry Point ; Startup Code must be linked first at Address at which it expects to run. AREA Reset, CODE, READONLY

25、 ARM ; Exception Vectors ; Mapped to Address 0. ; Absolute addressing mode must be used. ; Dummy Handlers are implemented as infinite loops which can be modified. Vectors LDR PC, Reset_Addr LDR PC, Undef_Addr LDR PC, SWI_Addr LDR PC, PAbt_Addr LDR PC, DAbt_Addr NOP ; Reserved Vector ; LDR PC, IRQ_Ad

26、dr LDR PC, PC, #-0 x0FF0 LDR PC, FIQ_Addr IF LEH_SETUP 0 EXTERN UndefHandler EXTERN SWIHandler EXTERN PAbtHandler EXTERN DAbtHandler EXTERN IRQHandler EXTERN FIQHandler ENDIF Reset_Addr DCD Reset_Handler Undef_Addr DCD UndefHandler SWI_Addr DCD SWI_Handler PAbt_Addr DCD PAbtHandler DAbt_Addr DCD DAb

27、tHandler DCD 0 ; Reserved Address IRQ_Addr DCD IRQHandler FIQ_Addr DCD FIQHandler IF LEH_SETUP = 0 IMPORT SWI_Handler ; SWI.s UndefHandler B UndefHandler ;SWIHandler B SWIHandler PAbtHandler B PAbtHandler DAbtHandler B DAbtHandler IRQHandler B IRQHandler FIQHandler B FIQHandler ENDIF ; Reset Handler

28、 EXPORT Reset_Handler Reset_Handler NOP ; Wait for OSC stabilization NOP NOP NOP NOP NOP NOP NOP ; Setup System Configuration (and SRAM Size) IF SCR0_SETUP = 1 LDR R0, =SCU_BASE LDR R1, =SCU_SCR0_Val STR R1, R0, #SCU_SCR0_OFS ORR R1, #0 x00000200 STR R1, R0, #SCU_SCR0_OFS ENDIF ; Setup Flash Memory

29、Interface (FMI) IF FMI_SETUP = 1 LDR R0, =FMI_BASE LDR R1, =FMI_BBSR_Val STR R1, R0, #FMI_BBSR_OFS LDR R1, =FMI_NBBSR_Val STR R1, R0, #FMI_NBBSR_OFS LDR R1, =(FMI_BBADR_Val:SHR:2) STR R1, R0, #FMI_BBADR_OFS LDR R2, =(FMI_NBBADR_Val:SHR:2) STR R2, R0, #FMI_NBBADR_OFS LDR R3, =FMI_CR_Val STR R3, R0, #

30、FMI_CR_OFS ; Write Write flash configuration command (60h) ; IF :DEF:BOOT_BANK1 MOV R0, R1, LSL #2 ; ELSE ; MOV R0, R2, LSL #2 ; ENDIF MOV R1, #0 x60 STRH R1, R0, #0 ; Write Write flash configuration confirm command (03h) LDR R2, =(FLASH_CFG_Val:SHL:2) ADD R0, R0, R2 MOV R1, #0 x03 STRH R1, R0, #0 E

31、NDIF ; Setup Clock IF CLOCK_SETUP = 1 LDR R0, =SCU_BASE ; LDR R1, =SCU_SYSSTATUS_Val ; STR R1, R0, #SCU_SYSSTAT_OFS ;Clear flag LDR R1, =0 x00020002 STR R1, R0, #SCU_CLKCNTR_OFS ; Select OSC as clk src NOP ; Wait for OSC stabilization NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP LDR R1, =0 x0003C019

32、; PLL to default STR R1, R0, #SCU_PLLCONF_OFS LDR R1, =SCU_PLLCONF_Val ; PLL to requested value STR R1, R0, #SCU_PLLCONF_OFS ; Wait until PLL is stabilized (if PLL enabled) IF (SCU_PLLCONF_Val:AND:0 x80000) != 0 PLL_Loop LDR R2, R0, #SCU_SYSSTAT_OFS ANDS R2, R2, #SYSSTAT_LOCK BEQ PLL_Loop ENDIF LDR

33、R1, =SCU_CLKCNTR_Val ; Setup clock control STR R1, R0, #SCU_CLKCNTR_OFS LDR R1, =SCU_PCGR0_Val ; Enable clock gating STR R1, R0, #SCU_PCGR0_OFS LDR R1, =SCU_PCGR1_Val STR R1, R0, #SCU_PCGR1_OFS ENDIF ; Setup Peripheral Reset IF P_RESET_SETUP != 0 LDR R1, =SCU_PRR0_Val STR R1, R0, #SCU_PRR0_OFS LDR R

34、1, =SCU_PRR1_Val STR R1, R0, #SCU_PRR1_OFS ENDIF ; Setup Stack for each mode LDR R0, =Stack_Top ; Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #UND_Stack_Size ; Enter Abort Mode and set its Stack Pointer MSR CPSR_c, #Mode_A

35、BT:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #ABT_Stack_Size ; Enter FIQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #FIQ_Stack_Size ; Enter IRQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #IRQ_Stack_S

36、ize ; Enter Supervisor Mode and set its Stack Pointer MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #SVC_Stack_Size ; Enter User Mode and set its Stack Pointer MSR CPSR_c, #Mode_USR ; IF :DEF:_MICROLIB ; EXPORT _initial_sp ; ELSE MOV SP, R0 SUB SL, SP, #USR_Stack_Size ; ENDIF ; Setu

37、p General purpose I/O ports (GPIO) IF GPIO_SETUP = 1 IF (SCU_PCGR1_Val:AND:0 x20000) != 0 ;SET GPIO3 LDR R0, =GPIO3_BASE LDR R1, =GPIO3_DIR_Val STR R1, R0, #GPIO_DIR_OFS LDR R1, =GPIO3_SEL_Val STR R1, R0, #GPIO_SEL_OFS LDR R0, =SCU_BASE LDR R1, =SCU_GPIOOUT3_Val STR R1, R0, #SCU_GPIOOUT3_OFS LDR R1,

38、 =SCU_GPIOIN3_Val STR R1, R0, #SCU_GPIOIN3_OFS LDR R1, =SCU_GPIOTYPE3_Val STR R1, R0, #SCU_GPIOTYPE3_OFS ENDIF ENDIF ; Setup Universal asynchronous receiver transmitter (UART) IF UART_SETUP != 0 IF (SCU_PCGR1_Val:AND:0 x8) != 0 ;SET UART0 LDR R0, =UART0_BASE LDR R1, =0 x0300 STR R1, R0, #UART_CR_OFS

39、 ;STOP UART0 UART0_Loop LDR R2, R0, #UART_FR_OFS ANDS R2, R2, #0 x8 CMP R2, #0 x8 BEQ UART0_Loop ;wait for UART0 free LDR R1, =0 x0000 STR R1, R0, #UART_LCR_OFS ;close FIFO LDR R1, =UART0_IBRD_Val STR R1, R0, #UART_IBRD_OFS LDR R1, =UART0_FBRD_Val STR R1, R0, #UART_FBRD_OFS LDR R1, =UART0_IFLS_Val S

40、TR R1, R0, #UART_IFLS_OFS LDR R1, =UART0_IMSC_Val STR R1, R0, #UART_IMSC_OFS LDR R1, =UART0_ICR_Val STR R1, R0, #UART_ICR_OFS LDR R1, =UART0_DMACR_Val STR R1, R0, #UART_DMACR_OFS LDR R1, =UART0_LCR_Val STR R1, R0, #UART_LCR_OFS LDR R1, =UART0_CR_Val STR R1, R0, #UART_CR_OFS ENDIF IF (SCU_PCGR1_Val:AND:0 x10) != 0 ;SET UART1 LDR R0, =UART1_BASE LDR R1, =