(完整word版)汽车尾灯设计

1、汽车尾灯设计 VHD语言-EDA课程设计(2009-06-03 17:30:10)标签:杂谈元件列化部分Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_ un sig ned.all;En tity tp isPort(clk:in std_logic;Left:in std_logic;Right:in std_logic;Brake:in std_logic;Night:in std_logic;Ld1,ld2,ld3:out std_logic;Rd1,rd2,rd3:out stdo gic);End;Archit

2、ecture bh of tp isSignal tmp0,tmp1,tmp2,tmp3,tmp4:std_logic;Sig nal err0,err1,err2,err3,err4,err5:stdo gic;sig nal bm:std_logic;BeginComp onent sz isPort(clk:in std_logic;Cp:out std_logic);End component;Component ctrl isPort(left,right,brake,night:in std_logic;Lp,rp,lr,brake_led,night_led:out std_lo

3、gic);End component;Component lc isPort(clk,lp,lr,brake,night:in std_logic;Ledl,ledb,ledn:out std_logic);End component;Component rc isPort(clk,rp,lr,brake,night:in std_logic;Ledr,ledb,ledn:out std_logic);End component;U1:sz port map(clk,bm);U2:ctrl port map(left,right,brake,night,tmp0,tmp1,tmp2,tmp3,

4、tmp4);U3:lc port map(clk,tmp0,tmp2,tmp3,tmp4,err0,err1,err2);U4:rc port map(clk,tmp1,tmp2,tmp3,tmp4,err3,err4,err5);Ld1=err0 and bm;Ld2=err1;Ld3=err2;Rd1=err3 and bm;Rd2=err4;Rd3=err5;End;汽车尾灯主控制模块 CTRL：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CTRL ISPORT(LEFT,RIGHT,BRAKE,NIGHT: IN STD_LOGIC;

5、LP,RP,LR,BRAKE_LED,NIGHT_LED: OUT STD_LOGIC);END ENTITY CTRL;ARCHITECTURE ART OF CTRL ISBEGINNIGHT_LED=NIGHT;BRAKE_LEDLP=0;RP=0;LRLP=0;RP=1;LRLP=1;RP=0;LR=0;误控制信号END CASE;END PROCESS;END ARCHITECTURE ART;时钟分频模块 SZ：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SZ IS-

6、 时钟输入- 定义八位标准逻辑位矢量数据类PORT(CLK: INSTD_LOGIC;CP: OUT STD_LOGIC);END ENTITY SZ;ARCHITECTURE ART OF SZ ISSIGNAL COUNT:STD_LOGIC_VECTORD(7OWNTO0); 型BEGINPROCESS(CLK)BEGINIF CLKEVENTANDCLK=1 THEN检测时钟上升沿COUNT=COUNT+1;END IF;END PROCESS;CP=COUNT(3);- 输出第五位END ARCHITECTURE ART;右边尾灯控制模块 RC：LIBRARY IEEE;USE IE

7、EE.STD_LOGIC_1164.ALL;ENTITY RC ISPORT(CLK,RP,LR,BRAKE,NIGHT: IN STD_LOGIC;LEDR,LEDB,LEDN: OUT STD_LOGIC);END ENTITY RC;ARCHITECTURE ART OF RC ISBEGINLEDB=BRAKE;LEDN=NIGHT;PROCESS(CLK,RP,LR)BEGINIF CLKEVENT AND CLK=1THEN - 检测时钟上升沿IF(LR=0) THENIF(RP=0) THENLEDR=0;ELSELEDR=1; END IF;ELSELEDR=0;END IF;END IF;END PROCESS;END ARCHITECTURE ART;左边尾灯控制模块 LC：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY LC ISPORT(CLK,LP,LR,BRAKE,NIGHT: IN STD_LOGIC; LEDL,LEDB,LEDN: OUT STD_LOGIC);END ENTITY LC;ARCHITECTURE ART OF LC ISBEGINLEDB=BRAKE;LEDN=NIGHT;PROCESS(CLK,LP,LR)BEGINIF CLKEVENTANDC