海大EDA实验1参考答案

1、百度文库让每个人平等地捉升口我 Laboratory Exercise 1 Switches, Lights, and Multiplexers ED实验参与答案 Parti library ieee; use parti is port(SW:instdogic_vector(17 downto 0); LEDR :out stdogic_vector(17 downto 0); end parti; architecture Behavior of parti is begin LEDR= SW; end Behavior; part 2 library ieee; use 2 to 1

2、multiplexer entity entity mux21 is port(in_x, in_y, in_s:instd_logic; out_m :out std_logic); end mux21; -a 2 to 1 multiplexer architecture architecture structural of mux21 is signal u, v :stdjogic; begin u = in_x and (not in_s); v = in_y and in_s ; out_m SW(0)z in_y=SW(8), in_s=SW(17), out_m=LEDR(0)

3、; U2: mux21 port map (in_x二SW，in_y=SW(9), in_s=SW(17), out_m=LEDR(l); U3: mux21 port map (in_x=SW(2)/ in-y=SW(10)/ in_s=SW(17)/ out_m=LEDR(2); U4: mux21 port map (in_x=SW(3), in-y=SW(ll)/ in_s=SW(17), out_m=LEDR(3); U5: mux21 port map (in_x=SW(4)/ in-y=SW(12)z in_s 二SW(17), out_m=LEDR(4); U6: mux21

4、port map (in_x=SW(5)/ in_y=SW(13)/ in_s=SW(17), out_m=LEDR(5); U7: mux21 port map (in_x=SW(6), in-y=SW(14)/ in_s=SW(17), out_m=LEDR(6); U8: mux21 port map (in_x=SW(7)/ in_y=SW(15)/ in_s 二SW(17), out_m=LEDR(7); end Structural; part3 library ieee; use 2 to 1 multiplexer entity entity mux21 is port(in_

5、x, in_y, in_s:instd_logic; out_m :out stdjogic); end mux21; -a 2 to 1 multiplexer architecture architecture structural of mux21 is signal signal_u, signal:stdjogic; begin signal_u = in_x and (not in_s); signal=in_y and in_s ; out_m signal_c); U4: mux21 port map (in_x=in5_u, in_y二in5_v, in_s=in5_s0,

6、out_m=signal_a); port map (in_x二in5_w, in_y=in5_xz in_s=in5_s0, out_m=signal_b); port map(in _x=signal_a,in_y=signal_b, in_s=in5_slz port map (in_x=signalc, in_y=in5_y/ in_s=in5_s2/ out_m=out5_m); end Structural; library ieee; -a 3bit 5 to 1 multiplexer entity entity mux51_3bit is port(SW :in stdogi

7、c_vector (17 downto 0); LEDR :out stdogic_vector (17 downto 0); LEDG :out std_logic_vector (2 downto 0); end mux51_3bit; -a 3bit 5 to 1 multiplexer architecture architecture structural of mux51_3bit is component mux51 port(in5_u in5_v, in5_w, in5_x, in5_y, in5_slz in5_s2, in5_s0:instdjogic; out5_m :

8、out stdjogic); end component; begin LEDRSW(0), in5_v=SW(3)/ in5_w=SW(6)/ ln5_x=SW(9), in5-y=SW(12)z in5_sO=SW(15),in5-sl=SW(16)/in5_s2=SW17), out5_m=LEDG(0); U2: mux51 port map (in5_u=SW(l), in5_v=SW4), in5_w=SW(7)/ in5_x=SW(10), in5-y=SW(13)/ in5_sO=SW(15),in5_sl=SW(16)，in5_s2=SW(17)/ out5_m=LEDG(l

9、); U3: mux51 port map (in5_u=SW(2)/ in5_v=SW(5)/ in5_w=SW(8)/ in5_x=SW(ll)/ in5_y=SW(14)z in5_sO=SW15),in5_sSW(16),in5_s2=SW(17), out5_m=LEDG(2); end structural; part4 library ieee; use 7-segment decoder entity entity decoder is port(decoder_in_3 :in std_logic_vector(2 downtoO); HEXO :out std_logic_

10、vector(0 to 6); end decoder; -a 7-segment decorder architecture architecture behavioral of decoder is begin process(decoderjn_3) begin case decoder_in_3 is when OO11= HEXO HEXO HEXO HEXO HexO SW,Seg二HEXO); Ul: mux51_seg7 port map(Mux51_seg7_in(17 downto 15)=SW(17 downto 15), Mux5l_seg7Jn(14 downto 1

11、2)=SW(11 downto 9), Mux5l_seg7Jn(11 downto 9)=SW(8 downto 6), Mux51_seg7Jn(8 downto 6)=SW(5 downto 3), Mux51_seg7Jn(5 downto 3)=SW(2 downto 0), Mux51_seg7Jn(2 downto 0)=SW(14 downto 12), Seg=HEXl); U2: mux51_seg7 port map(Mux51_seg7Jn(17 downto 15)=SW(17 downto 15), Mux5l_seg7 Jn(14 downto 12)=SW8 d

12、ownto 6)z Mux5l_seg7Jn(11 downto 9)=SW(5 downto 3), Mux51_seg7Jn(8 downto 6)=SW(2 downto 0), Mux51_seg7_in(5 downto 3)=SW仕4 downto 12), Mux51_seg7Jn(2 downto 0)=SW(ll downto 9), Seg 二HEX2); U3: mux51_seg7 port map(Mux51_seg7_in(17 downto 15)=SW(17 downto 15), Mux5l_seg7Jn(14 downto 12)=SW5 downto 3)

13、, Mux5l_seg7Jn(11 downto 9)=SW(2 downto 0), Mux51_seg7_in(8 downto 6)=SW(14 downto 12), Mux51_seg7_in(5 downto 3)=SW(11 downto 9), Mux51_seg7Jn(2 downto 0)=SW(8 downto 6), Seg=HEX3); U4: mux51_seg7 port map(Mux51_seg7Jn(17 downto 15)=SW(17 downto 15), Mux5l_seg7Jn(14 downto 12)=SW2 downto 0)z M ux5

14、l_seg7 J n (11 downto 9)=SW(14 downto 12), Mux51_seg7Jn(8 downto 6)=SW(11 downto 9), Mux51_seg7_in(5 downto 3)=SW(8 downto 6), Mux51_seg7Jn2 downto 0)=SW(5 downto 3), Seg=HEX4); end Behavior; A circuit that can select and display one of five characters library ieee; use mux51_seg7 is port(Mux51_seg7

15、Jn : in std_logic_vector(17 downto 0); Seg : out std_logic_vector(6 downto 0); end mux51_seg7; architecture Behavior of mux51_seg7 is component mux51_3bit port(S, U, V, W, X, Y : in std_logic_vector(2 downto 0); M : out std_logic_vector(2 downto 0); end component; component char_7seg port(C: in std_

16、logic_vector(2 downto 0); Display : out std_logic_vector(6 downto 0); end component; signal M : stdogic_vector(2 downto 0); begin M0: mux51_3bit port map(Mux51_seg7Jn(17 downto 15), Mux51_seg7Jn(14 downto 12),Mux51_seg7Jnll downto 9)f Mux51_seg7Jn(8 downto 6),Mux51_seg7_in(5 downto 3),Mux5i_seg7_in(

17、2 downto 0),M); HO: char_7seg port map(M, Seg); end Behavior; a 3bit mux5 library ieee; use 2 to 1 multiplexer entity entity mux21 is port(in_x, in_y, in_s:instd_logic; out_m :out std_logic); end mux21; -a 2 to 1 multiplexer architecture architecture structural of mux21 is signal signal_u, signal:st

18、djogic; begin signal_u = in_x and (not in s); signal_v = in_y and in_s ; out_m in5_u, in_y二in5_v, in_s=in5_s0, out_m=signal_a); U2: mux21 port map (in_x二in5_w in_y二in5_x, in_s=in5_s0, out_m=signal_b); U3: mux21 port map (in_x=signal_a, in_y=signal_b, in_s=in5_slz out_m=signal_c); U4: mux21 port map

19、(in_x=signal_c, in_y二in5_y, in_s=in5_s2, out_m=out5_m); end Structural; a 3bit 5 to 1 multiplexer library ieee; -a 3bit 5 to 1 multiplexer entity entity mux51_3bit is port(S, U, Vz W, X, Y : in stdogic_vector (2 downto 0); M : out std_logic_vector (2 downto 0); end mux51_3bit; -a 3bit 5 to 1 multipl

20、exer architecture architecture structural of mux51_3bit is component mux51 port(in5_u/ in5_v, in5_w, in5_x, in5_y, in5_slz in5_s2, in5_s0 :in std_logic; out5_m :out stdjogic); end component; begin Ul: mux51 in5_y=Y(0)/ U2: mux51 in5_y=Y(l)z U3: mux51 in5_y=Y(2)/ end structural; port map (in5_u=U(0)/

21、 in5_v=V(0)/ in5_w 二W(0)，in5_x=X(0), in5_s0=S(0), in5_sl=S(l)/ in5_s2=S(2), out5_m=M0); port map (in5_u=U(l)，in5-v=V(l)/ in5_w 二W(2)，in5_x=X(l), in5_s0=S(0)/ in5_sl=S(l), in5_s2=S(2)/ out5_m=M(l); port map (in5-u=U(2)/ in5_v=V(2)/ in5_w 二W(2), in5_x=X(2), in5_s0=S(0)/ in5_sl=S(l)/ in5-s2=S(2)/ out5_

22、m=M)； a 7-segment decoder library ieee; use 7-segment decoder entity entity char_7seg is port( C :in std_logic_vector(2 downto 0); Display :out std_logic_vector(6 downto 0); end char_7seg; -a 7-segment decorder architecture architecture behavioral of char_7seg is begin process(C) begin case C is whe

23、n ”000” when when 50” when = Display Display Display Display Display SW(17 downto 15)zD0=SW(2 downto O)ZD1=SW(2 downto 0),D2=SW(2 downto 0),D3=SW(14 downto 12), D4=SW(11 downto 9)/D5=SW(8 downto 6),D6=SW(8 downto 6)ZD7=SW(5 downto 3)/Seg=HEX0); Ul: mux81_seg7 port map(S=SW(17 downto 15)/D0=SW(2 down

24、to 0),Dl=SW(2 downto 0),D2=SW(14 downto 12),D3=SW(11 downto 9), D4=SW(8 downto 6),D5=SW(8 downto 6),D6=SW(5 downto 3),D7=SW2 downto O)/Seg=HEXl); U2: mux81_seg7 port map(S=SW(17 downto 15),D0=SW(2 downto O)ZD1=SW(14 downto 12),D2=SW(11 downto 9),D3=SW(8 downto 6), D4=SW(8 downto 6),D5=SW(5 downto 3)

25、,D6=SW(2 downto 0)zD7=SW(2 downto 0),Seg=HEX2); U3: mux81_seg7 port map(S=SW(17 downto 15),D0=SW14 downto 12)/D1=SW(11 downto 9),D2=SW(8 downto 6),D3=SW(8 downto 6), D4=SW(5 downto 3)ZD5=SW(2 downto 0)zD6=SW(2 downto 0),D7二SW(2 downto 0),Seg=HEX3); U4: mux81_seg7 port map(S=SW(17 downto 15)/D0=SW(ll

26、 downto 9)ZD1=SW(8 downto 6)ZD2=SW(8 downto 6),D3=SW(5 downto 3), D4=SW(2 downto 0),D5=SW(2 downto 0),D6=SW(2 downto 0)/D7=SW(14 downto 12)/Seg=HEX4); U5: mux81_seg7 port map(S=SW(17 downto 15)/D0=SW(8 downto 6)ZD1=SW(8 downto 6),D2=SW(5 downto 3),D3=SW(2 downto 0), D4=SW(2 downto 0)zD5=SW(2 downto

27、0),D6=SW(14 downto 12)ZD7=SW(11 downto 9)zSeg=HEX5); U6: mux81_seg7 port map(S=SW(17 downto 15)/D0=SW(8 downto 6),D1=SW(5 downto 3),D2=SW(2 downto 0)zD3=SW(2 downto 0), D4=SW(2 downto 0),D5二SW(14 downto 12),D6=SW(11 downto 9)ZD7=SW(8 downto 6),Seg=HEX6); U7: mux81_seg7 port map(S=SW(17 downto 15)/D0

28、=SW(5 downto 3),D1=SW(2 downto 0),D2=SW(2 downto 0),D3=SW(2 downto 0), D4=SW(14 downto 12),D5二SW(11 downto 9),D6=SW(8 downto 6)ZD7=SW(8 downto 6),Seg=HEX7); end Behavior; A circuit that can select and display one of eight characters library ieee; use mux81_seg7 entity entity mux81_seg7 is port(S, DO, Dlz D2, D3, D4, D5, D6, D7 : in stdogic_vector(2 downto 0); Seg