IDT71V3579YS85BGG中文资料

1、IDT71V3579YS85BGG中文资料Featuresx 128K x 36, 256K x 18 memory configurations xSupports fast access times:Commercial:7.5ns up to 117MHz clock frequency Commercial and Industrial:8.0ns up to 100MHz clock frequency 8.5ns up to 87MHz clock frequencyx LBO input selects interleaved or linear burst modexSelf-

2、timed write cycle with global write control (GW ), byte write enable (BWE ), and byte writes (BW x)x 3.3V core power supplyx Power down controlled by ZZ input x 3.3V I/OxOptional - Boundary Scan JTAG Interface (IEEE 1149.1compliant)xPackaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQ

3、FP), 119 ball grid array (BGA) and 165 fine pitch ball grid arrayPin Description SummaryDescriptionThe IDT71V3577/79 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,address and control registers. There are no registers in the data output path (flow-

4、through architecture). Internal logic allows the SRAM to gen-erate a self-timed write based upon a decision which can be left until the end of the write cycle.The burst mode feature offers the highest level of performance to the system designer, as the IDT71V3577/79 can provide four cycles of data f

5、or a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the s

6、ame cycle. If burst mode operation is selected (ADV =LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin.The IDT71V3577/79 SRAMs utilize

7、 IDTs latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA).A 0-A 17Address Inputs Input Synchronous CE Chip Enable Input Synchronous CS 0, CS

8、1Chip Selects Input Synchronous OE Output Enable Input Asynchronous GW Global Write Enable Input Synchronous BWEByte Write Enable Input Synchronous BW 1, BW 2, BW 3, BW 4(1)Individual Byte Write Selects Input SynchronousCLKClockInput N/A ADV Burst Address Advance Input Synchronous ADSC Address Statu

9、s (Cache Controller)Input Synchronous ADSP Address Status (Processor)Input SynchronousLBO Linear / Interleaved Burst Order Input DC TMS T est Mode Select Input Synchronous TDI Test Data Input Input SynchronousTCK Test Clock Input N/A TDOTest Data Output Output Synchronous TRST JTAG Reset (Optional)I

10、nput Asynchronous ZZSleep Mode Input Asynchronous I/O 0-I/O 31, I/O P1-I/O P4Data Input / Output I/O SynchronousV DD , V DDQ Core Power, I/O Power Supply N/A 128K X 36, 256K X 183.3V Synchronous SRAMs3.3V I/O, Flow-Through OutputsBurst Counter, Single Cycle DeselectIDT71V3577S IDT71V3579S IDT71V3577

11、SA IDT71V3579SAPin Definitions (1)NOTE:1.All synchronous inputs must meet specified setup and hold times with respect to CLK.Symbol Pin Function I/O Active DescriptionA 0-A 17Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CL

12、K and ADSC Low or ADSP Low and CE Low.ADSC Address Status (Cache Controller)I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the address registers with new addresses.ADSP Address Status (Processor)I LOW Synchronous Address Status from Processor

13、. ADSP is an active LOW input that is used to load the address registers with new addresses. ADSP is gated by CE .ADVBurst Address Advance ILOWSynchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter,controlling burst access after the initial address

14、 is loaded. When the input is HIGH the burst counter is not incremented; that is, there is no address advance.BWE Byte Write EnableI LOWSynchronous byte write enable gates the byte write inputs BW 1-BW 4. If BWE is LOW at the rising edge of CLK then BW x inputs are passed to the next stage in the ci

15、rcuit. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.BW 1-BW 4Individual Byte Write Enables I LOW Synchronous byte write enables. BW 1 controls I/O 0-7, I/O P1, BW 2 controls I/O 8-15, I/O P2, etc. Any active byte write causes all outputs to be disabled

16、.CE Chip Enable I LOW Synchronous chip enable. CE is used with CS 0 and CS 1 to enable the IDT71V3577/79. CE also gates ADSP .CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this input.CS 0Chip Select 0I HIGH Synchronous active HIGH chip select.

17、 CS 0 is used with CE and CS 1 to enable the chip.CS 1Chip Select 1I LOW Synchronous active LOW chip select. CS 1 is used with CE and CS 0 to enable the chip.GW Global Write Enable I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of C

18、LK. GW supersedes individual byte write enables.I/O 0-I/O 31I/O P1-I/O P4Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data output path is flow-through (no output register).LBOLinear Burst OrderILOWAsyn

19、chronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is selected.When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state while the device is operating.OE Output Enable I LOW Asynchronous output enable. When OE is LOW t

20、he data output drivers are enabled on the I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.TMS T est ModeSelect I N/A Gives input command for T AP controller. Sampled on rising edge of TDK. This pin has an internal pullup.TDI T est Data Input I N/A Se

21、rial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal pullup.TCK T est Clock I N/A Clock input of T AP controller. Each T AP event is clocked. T est inputs are captured on rising edge of TCK,while test outputs are driven from the falling edge of

22、TCK. This pin has an internal pullup.TDOT est DataOutput ON/ASerial output of registers placed between TDI and TDO. This output is active depending on the state of the T AP controller.TRSTJT AG Reset (Optional)I LOWOptional Asynchronous JT AG reset. Can be used to reset the T AP controller, but not

23、required. JT AG reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left floating. This pin has an internal pullup. Only available in BGA package.ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and

24、 power down the IDT71V3577/79 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull down.V DD Power Supply N/A N/A 3.3V core power supply.V DDQ Power Supply N/A N/A 3.3V I/O Supply.V SS Ground N/A N/A Ground.NCNo ConnectN/AN/ANC pins are not

25、electrically connected to the device.5280 tbl 02Functional Block DiagramA 0-ABW BW BW BW CS CS I/O 0-I/O I/O P1-I/O 5280drw 01ZZTMS TDI TCKTRST(Optional)TDO100 Pin TQFP Capacitance (T A = +25 C, f = 1.0mhz)Recommended Operating Temperature Supply VoltageAbsolute Maximum Ratings(1)NOTES:1.Stresses gr

26、eater than those listed under ABSOLUTE MAXIMUM RATINGS maycause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to abs

27、olute maximum rating conditions for extended periods may affect reliability.2.V DD terminals only.3.V DDQ terminals only.4.Input terminals only.5.I/O terminals only.6.This is a steady-state DC parameter that applies after the power supplies haveramped up. Power supply sequencing is not necessary; ho

28、wever, the voltage on any input or I/O pin cannot exceed V DDQ during power supply ramp up.7. T A is the instant on case temperature.Recommended DC Operating ConditionsNOTES:1.V IH (max) = V DDQ + 1.0V for pulse width less than t CYC/2, once per cycle.2.V IL (min) = -1.0V for pulse width less than t

29、 CYC/2, once per cycle.Symbol RatingCommercial & Industrial ValuesUnitV TERM(2)T erminal Voltage withRespect to GND-0.5 to +4.6VV TERM(3,6)T erminal Voltage withRespect to GND-0.5 to V DD VV TERM(4,6)T erminal Voltage withRespect to GND-0.5 to V DD +0.5VV TERM(5,6)T erminal Voltage withRespect to GN

30、D-0.5 to V DDQ +0.5VT A(7)CommercialOperating Temperature-0 to +70o CIndustrialOperating Temperature-40 to +85o CT BIAS T emperatureUnder Bias-55 to +125o CT STG StorageT emperature-55 to +125o C P T Power Dissipation 2.0W I OUT DC Output Current50mA5280 tbl 03Grade Temperature(1)V SS V DD V DDQ Com

31、mercial0C to +70C0V 3.3V5% 3.3V5% Industrial-40C to +85C0V 3.3V5% 3.3V5%5280 tbl 04Symbol Parameter Min.Typ.Max.Unit V DD Core Supply Voltage 3.135 3.3 3.465V V DDQ I/O Supply Voltage 3.135 3.3 3.465V V SS Supply Voltage000V V IH Input High Voltage - Inputs 2.0_V DD +0.3V V IH Input High Voltage - I

32、/O 2.0_V DDQ +0.3(1)V V IL Input Low Voltage-0.3(2)_0.8V5280 tbl 06Symbol Parameter(1)Conditions Max.Unit C IN Input Capacitance V IN = 3dV5pF C I/O I/O Capacitance V OUT = 3dV7pF5280 tbl 07NOTES:1. T A is the instant on case temperature.119 BGA Capacitance(T A = +25 C, f = 1.0mhz)Symbol Parameter(1

33、)Conditions Max.UnitC IN Input Capacitance V IN = 3dV7pFC I/O I/O Capacitance V OUT = 3dV7pF5280 tbl 07a165 fBGA Capacitance(T A = +25 C, f = 1.0mhz)Symbol Parameter(1)Conditions Max.UnitC IN Input Capacitance V IN = 3dV7pFC I/O I/O Capacitance V OUT = 3dV7pFPin Configuration 128K x 36100 TQFP Top V

34、iewNOTES:1.Pin 14 does not have to be directly connected to V SS as long as the input voltage is 2.Pin 64 can be left unconnected and the device will always remain in active mode.67C E S 0B W 4B W 3B W 2B W 1C S 1D DS SC L K W B W E O E AD S C D S P A D V 89I/O I/O I/O V V I/O I/O I/O I/O V V I/O I/

35、O V SS V I/O I/O V V I/O I/O I/O I/O V V I/O I/O I/O P214DDQ SS 13121110SS DDQ 98SS DD (2)76DDQ SS 5432SS DDQ 10P1V 15drw 02aPin Configuration 256K x 18100 TQFP Top ViewNOTES:1.Pin 14 does not have to be directly connected to V SS as long as the input voltage is 2.Pin 64 can be left unconnected and

36、the device will always remain in active mode.67C E S 0N C C B W 2B W 1C S 1D DS SC L K G W B W E O E AD S C A D S P A D V 89A 17N C N C L B O A 15A 14A 13A 12A 11V D DV S SA 0A 1A 2A 3A 4A 5V V SS I/O I/O I/O V SS V I/O I/O V SS V I/O I/O V V SS I/O I/O V SS V A 10NC V DDQ V SS NC I/O P1I/O 7I/O 6V

37、SS V DDQ I/O 5I/O 4V SS NC V DD ZZ (2)I/O 3I/O 2V DDQ V SS I/O 1I/O 0NC NC V SS V DDQ NC NC NCV SS (1)NC A 1602bN C N C1234567A V DDQ A 6A 4ADSP A 8A 16V DDQ B NC CS 0A 3ADSC A 9CS 1NC C A 7A 2V DD A 13A 17NC D I/O 8NC V SS NC V SS I/O 7NC E NC I/O 9V SS CE V SS NC I/O 6F V DDQ NC V SS OE V SS I/O 5

38、V DDQ G NC I/O 10ADV BW 2NC I/O 4H I/O 11NC V SS GW V SS I/O 3NC J V DDQ V DD NC V DD NC V DD V DDQ K NC I/O 12V SS CLK V SS NC I/O 2L I/O 13NC NC BW 1I/O 1NC M V DDQ I/O 14V SS BWE V SS NC V DDQ N I/O 15NC V SS A 1V SS I/O 0NC P NC I/O P2V SS A 0V SS NC I/O P1R NC A 5LBO V DD NC A 12V SS T NC A 10A

39、 15NCA 14A 11ZZ (3)UV DDQV DDQ5280drw 02dNC V SS V SS NC/TMS (2)NC/TDI (2)NC/TCK (2)NC/TDO (2)NC/TR ST (2,4)Pin Configuration 256K x 18, 119 BGAPin Configuration 128K x 36, 119 BGATop ViewTop ViewNOTES:1.R5 does not have to be directly connected to V SS as long as the input voltage is 2.These pins a

40、re NC for the S version or the JTAG signal listed for the SA version. Note: If NC, these pins can either be tied to V SS , V DD or left floating.3.T7 can be left unconnected and the device will always remain in active mode.1234567A V DDQ A 6A 4ADSP A 8A 16V DDQ B NC CS 0A 3ADSC A 9CS 1NC C A 7A 2V D

41、D A 12A 15NC D I/O 16I/O P3V SS NC V SS I/O P2I/O 15E I/O 17I/O 18V SS CE V SS I/O 13I/O 14F V DDQ I/O 19V SS OE V SS I/O 12V DDQ G I/O 20I/O 21BW 3ADV BW 2I/O 11I/O 10H I/O 22I/O 23V SS GW V SS I/O 9I/O 8J V DDQ V DD NC V DD NC V DD V DDQ K I/O 24I/O 26V SS CLK V SS I/O 6I/O 7L I/O 25I/O 27BW 4NC B

42、W 1I/O 4I/O 5M V DDQ I/O 28V SS BWE V SS I/O 3V DDQ N I/O 29I/O 30V SS A 1V SS I/O 2I/O 1P I/O 31I/O P4V SS A 0V SS I/O 0I/O P1R NC A 5LBO V DD NC A 13T NC NCA 10A 11A 14NCZZ (3)UV DDQV DDQNC V SS 5280drw 02cNC/TMS (2)NC/TDI (2)NC/TCK (2)NC/TDO (2)NC/TR ST (2,4)Pin Configuration 256K x 18, 165 fBGAP

43、in Configuration 128K x 36, 165 fBGANOTES:1.H1 does not have to be directly V SS as long as input voltage is 2.These pins are NC for the S version or the JTAG signal listed for the SA version. Note: If NC, these pins can either be tied to V SS , V DD or left floating.3.H11 can be left unconnected an

44、d the device will always remain in active mode.4.Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.1234567891011A NC (4)A 7CE 1BW 3BW 2CS 1BWE ADSC ADV A 8NC B NC A 6CS 0BW 4BW 1CLK GWOEADSPA 9NC (4)C I/O P3NC V DDQ V SS V SS V SS V SS V SS V DDQ NC I/O

45、P2D I/O 17I/O 16V DDQ V DD V SS V SS V SS V DD V DDQ I/O 15I/O 14E I/O 19I/O 18V DDQ V DD V SS V SS V SS V DD V DDQ I/O 13I/O 12F I/O 21I/O 20V DDQ V DD V SS V SS V SS V DD V DDQ I/O 11I/O 10G I/O 23I/O 22V DDQ V DD V SS V SS V SS V DD V DDQ I/O 9I/O 8H V SS (1)NC NC V DD V SS V SS V SS V DD NC NC Z

46、Z (3)J I/O 25I/O 24V DDQ V DD V SS V SS V SS V DD V DDQ I/O 7I/O 6K I/O 27I/O 26V DDQ V DD V SS V SS V SS V DD V DDQ I/O 5I/O 4L I/O 29I/O 28V DDQ V DD V SS V SS V SS V DD V DDQ I/O 3I/O 2M I/O 31I/O 30V DDQ V DD V SSV SS V SS V DD V DDQ I/O 1I/O 0N I/O P4NC V DDQ V SS NC/TRST (2,5)NC (4)NC V SS V D

47、DQ NC I/O P1P NCNC (4)A 5A 2NC/TDI (2)A 1NC/TDO (2)A 10A 13A 14NC (4)RLBONC (4)A 4A 3NC/TMS (2)A 0NC/TCK (2)A 11A 12A 15A 165280 tbl 171234567891011A NC (4)A 7CE 1BW 2NCCS 1BWE ADSC ADV A 8A 10B NC A 6CS 0NC BW 1CLK GWOEADSPA 9NC (4)C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC I/O P1D NC I/O 8V D

48、DQ V DD V SS V SS V SS V DD V DDQ NC I/O 7E NC I/O 9V DDQ V DD V SS V SS V SS V DD V DDQ NC I/O 6F NC I/O 10V DDQ V DD V SS V SS V SS V DD V DDQ NC I/O 5G NC I/O 11V DDQ V DD V SS V SS V SS V DD V DDQ NC I/O 4H V SS (1)NC NC V DD V SS V SS V SS V DD NC NC ZZ (3)J I/O 12NC V DDQ V DD V SS V SS V SS V

49、 DD V DDQ I/O 3NC K I/O 13NC V DDQ V DD V SS V SS V SS V DD V DDQ I/O 2NC L I/O 14NC V DDQ V DD V SS V SS V SS V DD V DDQ I/O 1NC M I/O 15NC V DDQ V DD V SSV SS V SS V DD V DDQ I/O 0NC N I/O P2NC V DDQ V SS NC/TRST (2,5)NC (4)NC V SS V DDQ NC NC P NCNC (4)A 5A 2NC/TDI (2)A 1NC/TDO (2)A 11A 14A 15NC

50、(4)RLBONC (4)A 4A 3NC/TMS (2)A 0NC/TCK (2)A 12A 13A 16A 175280 tbl 17aDC Electrical Characteristics Over the OperatingTemperature and Supply Voltage Range (1)DC Electrical Characteristics Over the OperatingTemperature and Supply Voltage Range (V DD = 3.3V 5%)AC Test LoadAC Test Conditions(V DDQ = 3.

51、3V)NOTE:1.The LBO , TMS, TDI, TCK and TRST pins will be internally pulled to V DD and the ZZ in will be internally pulled to V SS if they are not actively driven in the application.NOTES:1.All values are maximum guaranteed values.2.At f = f MAX, inputs are cycling at the maximum frequency of read cy

52、cles of 1/t CYC while ADSC = LOW; f=0 means no input lines are changing.3.For I/Os V HD = V DDQ - 0.2V, V LD = 0.2V. For other inputs V HD = V DD - 0.2V, V LD = 0.2V.5280drw 03Symbol ParameterTest ConditionsMin.Max.Unit |I LI |Input Leakage CurrentV DD = Max., V IN = 0V to V DD _5A |I LI |ZZ , LBO a

53、nd JTAG Input Leakage Current (1)V DD = Max., V IN = 0V to V DD_30A |I LO |Output Leakage Current V OUT = 0V to V DDQ , Device Deselected _5A V OL Output Low Voltage I OL = +8mA, V DD = Min._0.4V V OHOutput High VoltageI OH = -8mA, V DD = Min.2.4_V5280 tbl 08Symbol ParameterTest Conditions7.5ns8ns 8

54、.5ns Unit Coml OnlyComl Ind Coml Ind I DD Operating Power Supply Current Device Selected, Outputs Open, V DD = Max.,V DDQ = Max., V IN V IH or Device Deselected, Outputs Open, V DD = Max.,V DDQ = Max., V IN V HD or Full Sleep Mode Supply CurrentZZ V HD, V DD = Max.3030353035mA5280 tbl 09Input Pulse

55、Levels Input Rise/Fall Times Input Timing Reference Levels Output Timing Reference Levels AC T est Load0 to 3V 2ns 1.5V 1.5V See Figure 15280 tbl 10?tCD (Typical,ns)Capacitance (pF)5280drw 05Synchronous Truth Table (1,3)NOTES:1.L = V , H = V , X = Dont Care.OperationAddress Used CECS 0CS 1ADSPADSCAD

56、VGWBWEBW xOE (2)CLK I/O Deselected Cycle, Power Down None H X X X L X X X X X HI-Z Deselected Cycle, Power Down None L X H L X X X X X X HI-Z Deselected Cycle, Power Down None L L X L X X X X X X HI-Z Deselected Cycle, Power Down None L X H X L X X X X X HI-Z Deselected Cycle, Power Down None L L X

57、X L X X X X X HI-Z Read Cycle, Begin Burst External L H L L X X X X X L D OUT Read Cycle, Begin Burst External L H L L X X X X X H HI-Z Read Cycle, Begin Burst External L H L H L X H H X L D OUT Read Cycle, Begin Burst External L H L H L X H L H L D OUT Read Cycle, Begin Burst External L H L H L X H L H H HI-Z Write Cycle, Begin Burst External L H L H L X H L L X D IN Write Cycle, Begin Burst External L H L H L X L