(完整word版)EDA-常见实例源程序代码vhdl

1、第 4 章 用 VHDL 程序实现常用逻辑电路4.1 组合逻辑电路设计4.1.1 基本逻辑门 library ieee;use iee.std_logic_1164.all;entity jbm isport(a,b: in bit;f1,f2,f3,f4,f5,f: out bit);end jbm;architecture a of jbm isbeginf1=a and b;- 构成与门f2=a or b;- 构成或门f=not a;- 构成非门f3=a nand b;- 构成与非门f4=a nor b;- 构成异或门f5=not(a xor b); -构成异或非门即同门 end;4.1

2、.2 三态门library ieee;use ieee.std_logic_1164.all;entity tri_s isport(enable: in std_logic;datain: in std_logic_vector(7 downto 0); dataout: out std_logic_vector(7 downto0); end tri_s;architecture bhv of tri_s isbeginprocess(enable,datain)beginif enable=1 then dataout=datain;elsedataout=ZZZZZZZZ;end if

3、;end process;end bhv;4.1.3 3-8 译码器library ieee;use ieee.std_logic_1164.all;entity decoder3_8 isport(a,b,c,g1,g2a,g2b: in std_logic;y: out std_logic_vector(7 downto 0);end decoder3_8;architecture a of decoder3_8 issignal dz:std_logic_vector(2 downto 0);begindz yy=XXXXXXXX; end case;elseend if;end pro

4、cess;4.1.4 优先编码器library ieee;use ieee.std_logic_1164.allentity coder isport(din: in std_logic_vector(0 to 7);output: out std_logic_vector(0 to 2);end coder;architecture behave of coder issignal sint: std_logic_vevtor(4 downto 0);beginprocess(din)beginif (din(7)=0) then output = 000 ;elsif (din(6)=0)

5、 then output = 100 ;elsif (din(5)=0) then output = 010 ;elsif (din(4)=0) then output = 110 ;elsif (din(3)=0) then output = 001 ;elsif (din(2)=0) then output = 101 ;elsif (din(1)=0) thenoutput = 011 ;elseoutput led7s led7s = 0000110 ;led7s = 1011011 led7s = 1001111 led7s = 1100110 led7s = 1101101 led

6、7s = 1111101 led7s = 0000111 led7s = 1111111 led7s = 1101111 led7s = 1110111 led7s = 1111100 led7s = 0111001 led7s = 1011110 led7s = 1111001 led7s when 0011 =when 0100 =when 0101 =when 0110 =when 0111 =when 1000 =when 1001 =when 1010 =when 1011 =when 1100 =when 1101 =when 1110 =when 1111 = when othe

7、rs = end case;end process; end behave;4.1.6 二 -十进制 BCD 译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity bcdymq isport(din : in integer range 15 downto 0;a,b : out integer range 9 downto 0); end;architecture fpq1 of bcdymq isbeginp1: process(din)begin if din10 thena =d

8、in; b =0;elsea =din-10;bb+c0 then d=a-(b+c0); c1=0;elsec1=1; d=(10000)-(b+c0-a); end if;end process ;end ;4.2 时序逻辑电路设计4.2.1 触发器RS 触发器library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity rsff is port(r,s,clk:in std_logic;q,qb:buffer std_logic); end rsff;architecture rsff_ar

9、t of rsff is signal q_s,qb_s:std_logic;begin process(clk,r,s) beginif (clkevent and clk=1) thenif (s=1 and r=0) thenq_s=0 ;qb_s=1 ;elsif (s=0 and r=1) then q_s = 1 ; qb_s = 0 ;elsif (s=0 and r=0) then q_s = q_s; qb_s = qb_s;end if;end if;q_s = q_s; qb_s = qb_s;end process;end rsff_art;同步复位 D 触发器libr

10、ary ieee;use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity syndff is port(d,clk,reset:in std_logic;q,qb:out std_logic); end syndff; architecture dff_art of syndff is begin process(clk) beginif (clkevent and clk=1) then if (reset=0) then q=0; qb=1;elseq=d;qb=not q; end if; end if;end

11、 process;end dff_art;JK 触发器library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity asynjkff is port(j,k,clk,set.reset:in std_logic; q,qb:out std_logic);end asynjkff;architecture jkff_art of asynjkff is singal q_s,qb_s:std_logic;begin process(clk,set,reset) beginif (set=0 and

12、reset=1 ) then q_s=1; qb_s=0;elsif (set=1 and reset=0 ) thenq_s=0;qb_s=1;elsif (clkevent and clk=1) then if (j=0 and k=1 ) then q_s=0; qb_s=1;elsif (j=1 and k=0 ) then q_s=1; qb_s=0;elsif (j=1 and k=1 ) then q_s=not q_s; qb_s=not qb_s;end if;end if; q= q_s; qb= qb_s;end process;end jkff_art;T 触发器lib

13、rary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity tff isport(t,clk: in std_logic; q: out std_logic);end; architecture tff_art of tff is signal q_temp: std_logic;- 当 T=1 时 T 触发器具有2 分频的功能begin p1:process(clk) begin if rising_edge(clk) then if t=1 thenq_temp=not q_temp; elseq_t

14、emp=q_temp;end if;end if;q=q_temp;end process; q=q_temp;end tff_art;4.2.2 计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 ISport( clk: in std_logic;q: out std_logic_vector(3 downto 0);end cnt4;architecture behave of cnt4 issignal q1: std_logic_vector(3 downto

15、0); beginprocess(clk)beginif (clkevent and clk = 1) then q1=q1+1;end if;end process;q0);elsif (clkevent and clk = 1) then if en=1thenif updown=0thenif cqi0);end if;elseif cqi0 then cqi:=cqi-1;else cqi:=(others=1);end if;end if;end if;end if;cq=cqi;end process;-计数器异步复位-检测时钟上升沿-检测是否允许计数（同步使能）- 允许计数 ,检

16、测是否小于 9-大于 9，计数值清零- 检测是否大于 0- 否则，计数值置 1- 将计数值向端口输出end behave;4.2.3 分频器 library ieee; use std_logic_1164.all; use std_logic_unsigned.all;entity freq1 isport(clk: in std_logic;d: in std_logic_vector(7 downto 0); fout: out std_logic);end; architecture one of dvf issignal full: std_logic; begin p_reg:pr

17、ocess(clk)variable cnt8: std_logic_vector(7 downto 0);begin-检测时钟上升沿if clk event and clk= 1thenif cnt8= then cnt8:=d; full= 1;else cnt8:=cnt8+1; full= 0;end if;end if;end process p_reg;p_div:process(full)variable cnt2: std_logic;beginif fullevent and full=1 then cnt2:=not cnt2;if cnt2=1thenfout=1;els

18、efout reg (0) = c0 ; reg (7 downto 1) = reg (6 downto 0); cy reg (0) = reg (7); reg (7 downto 1) reg (7) = reg (0);reg (6 downto 0) reg (7) = C0 ;reg (6 downto 0) = reg (7 downto 1); cy reg (7 downto 0) reg= reg ; cy= cy ;end case;end if;end process;qb(7 downto 0) = reg (7 downto 0); cn = cy;end beh

19、av;4.3 状态机逻辑电路设计4.3.1 一般状态机设计-带进位循环左移-自循环左移-自循环右移-带进位循环右移-加载待移数- 保持-移位后输出library ieee;use ieee.std_logic_1164.all;entity s_machine isport ( clk,reset: in std_logic;state_inputs : in std_logic_vector(0 to1); comb_outputs : out integer range 0 to 15 ); end s_machine;architecture behv of s_machine is t

20、ype fsm_st is (s0, s1, s2, s3); signal current_state, next_state: fsm_st; beginreg: process(reset,clk)beginif reset = 1 thencurrent_state = s0;elsif clk=1 and clkevent then current_state comb_outputs= 5; if state_inputs = 00 then next_state=s0;elsenext_state comb_outputs= 8; if state_inputs = 00 the

21、n next_state=s1;elsenext_state comb_outputs= 12; if state_inputs = 11 then next_state = s0;elsenext_state comb_outputs = 14; if state_inputs = 11 then next_state = s3;elsenext_state = s0;end if;end case;end process;end behv;4.3.2 状态机的应用 library ieee; use ieee.std_logic_1164.all; entity asm_led ispor

22、t(clk,clr : in std_logic;led1,led2,led3:out std_logic);end;architecture a of asm_led istype states is (s0,s1,s2,s3,s4,s5);- 对状态机的状态声明signal q: std_logic_vector( 0 to 2);signal state : states;beginp1: process(clk,clr)beginif(clr=0)thenstate state state state state state state state=s0;end case;end if

23、;end process p1;p2: process (clr,state)beginif(clr=0) thenled1=0;led2=0; led3 led1=1;led2=0;led3 led1=0;led2=1;led3 led1=0;led2=1;led3 led1=0;led2=0;led3 led1=0;led2=0;led3 led1=0;led2=0;led3 null;end case; end if;end process p2;end ;第 6 章 EDA 仿真技术应用实例 6.1带使能和片选端的 16：4 线优先编码器设计 子模块设计源代码：library ieee

24、;use ieee.std_logic_1164.all;entity pencoder isport(d:in std_logic_vector(7 downto 0); ei:in std_logic;-ei:enable inputgs,eo:out bit;-gs:chip select output;eo:enable outputq2,q1,q0:out std_logic);end pencoder;architecture encoder of pencoder is beginprocess(d)begin if(d(0)=0 and ei=0)then q2=1;q1=1;

25、q0=1; gs=0;eo=1;elsif(d(1)=0 and ei=0)then q2=1;q1=1;q0=0; gs=0;eo=1;elsif(d(2)=0 and ei=0)then q2=1;q1=0;q0=1; gs=0;eo=1;elsif(d(3)=0 and ei=0)then q2=1;q1=0;q0=0; gs=0;eo=1;elsif(d(4)=0 and ei=0)then q2=0;q1=1;q0=1; gs=0;eo=1;elsif(d(5)=0 and ei=0)then q2=0;q1=1;q0=0; gs=0;eo=1;elsif(d(6)=0 and ei

26、=0)then q2=0;q1=0;q0=1; gs=0;eo=1;elsif(d(7)=0 and ei=0)then-d7 prioty encoderq2=0;q1=0;q0=0;gs=0;eo=1; elsif(ei=1)thenq2=1;q1=0;q0=1; gs=1;eo=1;0)then q2=1;q1=1;q0=1; gs=1;eo=0; end if;end process; end encoder;6.27 段显示译码器设计 译码器设计源代码： library ieee; use ieee.std_logic_1164.all;entity decoder47 is por

27、t(lt,ibr,ib_ybr:in bit;a: in std_logic_vector(3 downto 0); y:out std_logic_vector(6 downto 0); end decoder47;architecture art of decoder47 is beginprocess(lt,ibr,ib_ybr,a)variable s: std_logic_vector(3 downto 0);begins:=a(3)&a(2)&a(1)&a(0);-检查七段显示管是否正常if lt=0 and ib_ybr=1 theny=1111111;elsif ibr=0 a

28、nd a=0000 then yyyyyyyyyyyyyyyyy=0000000;end case;end if;end process;end art;6.3 带异步清零端的 12 位二进制全加器设计子模块源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0); s: out std_logic_vector(3 downto 0);

29、cout:out std_logic);end adder4b;architecture art of adder4b issignal sint:std_logic_vector(4 downto 0); signal aa,bb:std_logic_vector(4 downto 0);beginprocess(clr)beginif clr=1thensint=00000;elseaa=0&a;bb=0&b; sint=aa+bb+cin;end if; s=sint(3 downto 0); coutclr,cin=cin,a=a(3 downto 0),b=b(3 downto 0)

30、, s=s(3 downto 0),cout=carry_out1);u2:adder4b port map(clr=clr,cin=carry_out1,a=a(7 downto 4),b=b(7 downto 4),s=s(7 downto 4),cout=carry_out2);u3:adder4b port map(clr=clr,cin=carry_out2,a=a(11 downto 8),b=b(11 downto 8), s=s(11 downto 8),cout=cout);end art;6.4 带异步清零 /置位端的 JK 触发器设计 带异步清零 /置位端的 JK 触发器

31、源程序如下： library ieee;use ieee.std_logic_1164.all; entity jkff_logic is port(j,k,clk,clr,set:in std_logic;q:out std_logic); end jkff_logic; architecture art of jkff_logic is signal q_s:std_logic;begin process(clk,clr,set,j,k) beginif set=0 then q_s=1;- 异步置位elsif clr=1 then q=0;- 异步复位elsif clkevent and

32、 clk=1 then if (j=0) and (k=1) then q_s=0;elsif(j=1) and (k=0) thenq_s=1;elsif(j=1) and (k=1) then q_s=not q_s;end if;end if; q=q_s;end process;end art;6.5 4 位锁存器设计 子模块设计源代码： library ieee;use ieee.std_logic_1164.all;entity latch1b is port(d: in std_logic;ena: in std_logic;- 使能端q: out std_logic);end

33、latch1b;architecture art of latch1b isbegin process(d,ena) begin if ena=1 then q=d;end if;end process;end art;元件声明程序包设计源代码：library ieee;use ieee.std_logic_1164.all;package my_package is component latch1port(d:in std_logic;ena:in std_logic;q: out std_logic);end component; end;顶层模块设计源代码：library ieee;u

34、se ieee.std_logic_1164.all;use work.my_package.all;-使用用户自定义的程序包entity latch4d isport(d: in std_logic_vector(3 downto 0);oen: in bit;q:out std_logic_vector(3 downto 0);end latch4d;architecture one of latch4d issignal sig_save:std_logic_vector(3 downto 0);begin getlatch:for n in 0 to 3 generate-用 for_

35、generate 语句循环例化 4 个 1 位锁存器latchx:latch1 port map(d(n),g,sig_save(n); -关联end generate;q=sig_save when oen=0else ZZZZ; 1end one;6.6 32 进制多样型计数器设计(1) 32 进制同步加法计数器源程序32 进制同步加法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_plus is port(clk,clr:in std_logi

36、c;dout0,dout1: out std_logic_vector(3 downto 0); end;architecture art of counter_plus issignal d0,d1:std_logic_vector(3 downto 0);-d0 代表个位， d1 代表十位beginprocess(clk,clr,)beginif clr=1then d10);d0=0000;- 同步清零elsif clkevent and clk=1 then if(d1=3 and d0=1)then d1=0000;d0=0000;- 计数到 32 时清零elsif(d0=1) th

37、end0=0000; d1=d1+1;else d0=d0+1;end if;end if; dout1=d1;dout0=d0;end process;end art;(2) 32 进制同步减法计数器源程序32 进制同步减法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_sub is port(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0);end;archite

38、cture art of counter_sub is-d0 代表个位， d1 代表十位-异步清零- 设定容量 31signal d0,d1:std_logic_vector(3 downto 0); beginprocess(clk,clr)beginif clr=1 then d1=0000;d0=0000;elsif clkevent and clk=1 then if(d1=0 and d0=0) then d1=0011;d0=0001;elsif(d0=0) then d0=0001;d1=d1-1;else d0=d0-1;d1=d1;end if;end if;dout1=d1

39、;dout0=d0;end process;end art;(3)32 进制同步可逆计数器源程序32 进制同步可逆计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_reversible isport(clk,clr,s:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0);-s=1 加法计数， s=0 减法计数end;architecture art of counter_reversib

40、le is signal d0,d1:std_logic_vector(3 downto 0);beginprocess(clk,clr,s)beginif clr=1then d1=0000;d0=0000;elsif (clkevent and clk=1 )thenif s=1 thenif(d1=3 and d0=1) thend1=0000;d0=0000;elsif(d0=1) then d0=0000; d1=d1+1;else d0=d0+1; end if;elsif s=0 then if(d1=0 and d0=0)then d1=0011; d0=0001;elsif(

41、d0=0) then d0=0001; d1=d1-1;elsed0=d0-1; d1=d1;end if;end if;end if;dout1=d1;dout0=d0;end process;end art;(4)32 进制异步加法计数器源程序 32 进制异步加法计数器源程序如下： 子模块 D 触发器源程序设计。 library ieee;use ieee.std_logic_1164.all;-d0 代表个位， d1 代表十位-异步清零-计数到 31 时清零-设定容量 31entity dffr isport(clk,clr,d: in std_logic;q,qb:out std_logic);end;architecture art of dffr issignal qin:std_logic;beginq=qin; qb=not qin; process(clk,clr)beginif clr=1 then qin=0;elsif(clkevent and clk=1)then qin=d;end if;end process;end art; 顶层异步加法计数器源程序设计。 library ieee;use ieee.std_logic_1164.all;entity counter_a is- 异步加法计数器port(clk,clr:in std_log