testbanch+Verilog在Modelsim实现3分频及5分频

1、用Verilog语言写的三分频 电路/上升沿触发的分频设计 module three(clkin, clkout);in put clk in;/定义输入端口 output clkout;/ 定义输出端？ reg 1:0 step1, step;always (posedge clkin)beg incase (step)2b00: stepv=2b01;2b01: stepv=2b10;2b10: stepv=2b00; default :stepv=2b00;endcaseendalways (n egedge clkin)beg incase (step1)2b00: step1=2b0

2、1;2b01: step1=2b10;2b10: step1=2b00; default :step1=2b00;endcaseendassign clkout=(step1|step11); en dmoduleTestbanch :timescalel ns/100ps module div3_tb ;wire clkout;reg clki n ;wire 1:0 step1, step;in itialbegi nclki n=0;endalways #2clki n=clk in;div3 DUT ( .clki n (clki n), .clkout (clkout), .step

3、1(step1), .step(step);en dmodule用Verilog 语言写五分频电路，占空比为50%:module div_5 ( clkin ,rst,clkout ); in put clk in ,rst;output clkout;reg 2:0 stepl, step2; always (posedge clkin ) if(!rst) step1=3b000;else beg in case (step1) 3b000: step1=3b001; 3b001: step1=3b011; 3b011: step1=3b100; 3b100: step1=3b010; 3

4、b010: step1=3b000; default:step1=3b000; endcase endalways (n egedge clkin ) if(!rst)step2=3b000;else beg in case (step2) 3b000: step2=3b001; 3b001: step2=3b011; 3b011: step2=3b100; 3b100: step2=3b010; 3b010: step2=3b000; default:step2=3b000;endcaseendassign clkout=step10|step20;en dmoduleTestbanch:module div5_tb ; reg rst ;reg elk in ; wire clkout ;wire 2:0 step1, step2; in itialbeg inclki n=0;endalways #10 clki n=clk in;in itial beg inrst=0;#20 rst=1; #2000 $fini sh;enddiv5DUT (.rst (rst ), .clk