电子方面中英文对照翻译

1、山东理工大学 毕业设计（外文翻译材料）学 院：专 业：学生姓名：指导教师：电气与电子工程学院电子信息科学与技术王寿刚魏芹芹Automatic generation of intelligent instruments for IEEE 1451 AbstractIn this work we present the design of a smart transducers interface module (STIM) that meets the IEEE 1451 normative. The improvement of this prototype is that it can wo

2、rk with any configuration of transducers without the necessity of changing the software and hardware of the STIM. The system automatically adapts its functions from the transducers electronic data sheets (TEDS). We only need to write the appropriate TEDS of our transducers configuration in a non-vol

3、atile memory of the STIM. We also have developed a PC TEDS editor that allows us to introduce them in a friendly way in a PC and save them into the STIM through the parallel port.Keywords:Intelligent control; Smart transducer interface; Distributed measurement and control; Plug-and-play; Network pro

4、tocols1. Introduction Nowadays the transducers available in the market have many different ways of producing their outputs (420 mA, frequency output, voltage output, etc.). Because of this diversity the development of instrumentation systems that involve transducers with different types of interface

5、 becomes complex, expensive and laborious. This means a drawback for designers, transducer manufacturers and final users. The development of the standard IEEE 1451 1 and 2 intends to normalize and simplify the interconnection between transducer systems using networks, such as Ethernet 3 or CAN 4. Th

6、is normative gives very useful guidelines to make interconnection of transducers to instruments and networks easy and standard 5 and 6. The standard is divided in two parts: One part that describes the smart transducer interface module (STIM), giving rules for organising the transducers in channels,

7、 the definition of a standard connector (signals and timings) and the transducer electronic data sheets (TEDS). This last item is very important because they include complete information about the transducers and allow a lot of interesting features to be introduced, such as Plug-and-Play 7 and hot s

8、tart-up connection of nodes in the network. And another part that defines the network capable application processor (NCAP), the element that connects the STIM to the specific network used in each system. This element reads the TEDS from the STIM and uses them to notify the system about the available

9、 resources and to manipulate data from/to the STIM. Big companies in the electronics industry are already working in the development and commercialization of STIMs 8 and NCAPs 9 mainly for Ethernet based networks. Being this implication an important leap forward for the IEEE 1451 standard, the STIM

10、still is an element designed and produced for each specific application to be considered.2. Starting point The work presented is the consequence of the evolution of our investigations, during the two last years, on the development of complete nodes according to the IEEE 1451 standard. Each node incl

11、udes two subsystems, a STIM and an NCAP.The NCAP has been specifically designed for a CAN network.The first version of the STIM was generated by strictly following the philosophy of the IEEE 1451 standard. This first STIM was designed for a system composed by a temperature sensor and an actuator for

12、med by 6 LEDs, and was developed using and FPGA as a controller. After this first prototype we made a new design using a small microcontroller instead the FPGA. This alternative is much more flexible and implies a smaller development time.Despite the flexibility of using a microcontroller to impleme

13、nt the STIM, it still remains a problem in the development of real systems. The software of the microcontroller must be specifically designed for each application, depending on the transducers used in each node. Moreover, the hardware may be different depending on these transducers.3. Automatic gene

14、ration of STIMs From this starting point we established a new goal that represents an important improvement. The idea is simple: automatically generate the STIM from the specific system TEDS. In other words, we have designed and implemented a specific hardware and, with the information extracted fro

15、m the transducers TEDS, our tools develop the STIM software that suits the specific configuration of transducers in each application.3.1. Controller The STIM controller is based in a small analog devices data acquisition system integrated in a single chip. The most remarkable feature of this chip is

16、 that it includes a microcontroller core (8052), a precision 12-bit multiplexed (8 channels) analog to digital converter (ADC) with autocalibration and temperature sensor, and a two digital to analog converter (DAC). There are three blocks of memory in the chip: 8 Kbytes FLASH ROM for program, 640 b

17、ytes FLASH for data and 256 bytes RAM also for data. Moreover the chip has an external bus that allows the expansion of memory up to 16 Mbytes (this will be helpful for big TEDS). One of the microcontroller (C) ports is used to implement the standard digital connector to the NCAP. As can be seen in

18、Fig. 1, the complete STIM control circuitry is very simple and is made with only the ADuC812, a 512 Kbytes NVRAM memory, and registers to demultiplex the address/data bus of the ADuC812. Fig. 1. Block diagram of the STIM.Other facilities of the ADuC812 are interrupt dealing and integrated timers tha

19、t allow the generation of basetimes to implement some characteristics of the normative such as channel measurement repetitions or sequences generation.3.2. Memory organization One of the crucial points of the design is the memory organization. That is, which kind of data we need to store and how to

20、distribute them between the internal C memory and the NVRAM. We have to take in mind that the software of the C will be the same independently of the specific transducers. The only thing that controls the STIM functions are the TEDS, so in the memory system we will store information that the program

21、 on the C will use, together with the TEDS information.The C memory is organised as follows:8 Kbytes FLASH: The program that controls the system. We had to make the software in assembler in order to minimize code size, because we wanted to use exclusively the internal memory for code.640 bytes of da

22、ta FLASH: Information about the type of each channel (up to 255 channels) and also the size of the corresponding buffer in the external NVRAM. It is organized in two sections, and it is permanent once the system has been configured. See Table 1.Table 1. Organisation of the internal FLASHSectionInfor

23、mationPagesANumber of channels in the system (channel 0)0128Number of bytes in buffer per channel (1255).BType of channel (1255)129160Each page is 4 bytes long.Full-size table256 bytes RAM: For stack and the necessary program data variables. The organization of the NVRAM gets much more complicated w

24、hen the system has to offer good performances. The data that reside in the NVRAM memory are grouped in seven sections. In Table 2 we show these sections.Table 2. Organisation of the NVRAMSectionNVRAM informationAddressAStatus and mask registers for each channel. Defined by the normative0000-07FFBOne

25、 control register for each channel0800-08FFCModule address and address in module for each channel: Two bytes containing I2C address for each channel0900-0AFFDIndex of addresses for buffers and TEDS blocks of each channel. Four bytes each0B00-22FFEBuffer counters. Two bytes per channel to know the nu

26、mber of bytes already stored in each buffer2300-24FFFBuffers002500-03FFFFGTEDS040000-07FFFFFull-size tableTable options Read access of the internal memory is faster than in the external NVRAM, for this reason we save the most frequently used information in the internal data flash memory. Note that,

27、once the setup of the STIM is carried out, the information in this section (Table 1) is fixed and never changes. The location of the rest of the information in the NVRAM is derived from two factors: size of the data structure and/or data that must be written frequently (write operations in flash are

28、 far hardest than read operations). Note that the reserved space to status, mask and control registers in the NVRAM is independent of the number of channels. We have decided to “reserve” space for 255 channels. In this way the searching algorithms are simple and save an indexed table.3.3. Sensor and

29、 actuator modules Some additional modules have been developed to allow the connection of up to 255 channels of any type in order to make the system the most flexible and versatile within the standard. The channels are connected through different stackable modules, depending on the type of channel. T

30、hree different modules have been implemented:1.Analog inputs, up to 32 channels per module.2.Analog outputs, up to 32 channels per module.3.Digital channels (input and output), 16 lines per module. The first two types of modules are basically analog multiplexers that redirect the input/output signal

31、s of the transceivers to the analog input/output lines of the ADuC, As an example, in Fig. 2 we show the block diagram of the analog input module. Fig. 2. Block diagram of an analog sensor module. In the case of digital channels, the module is based in a small and economical C. The aim of this organ

32、ization, in the digital case, is to provide a method to define channels grouping lines of input/output, and to release from this work the ADuC.The communication between the STIM controller and the modules are made via an I2C bus. This communication consists of the selection of the channel to be meas

33、ured or activated. In the case of digital channels, in addition to this, the information of the transducers is also transmitted via I2C.This solution optimizes the utilization of the C ports, and simplifies the hardware connections.We can make any combination of these modules, stacking them over a S

34、TIM controller. The are only two hardware restrictions:1.No more than 255 channels (normative restriction).2.The buffer size needed by the transducers can not exceed the total buffer size available in the NVRAM.4. STIM software The basic idea of our design is that the STIM controller adapts its work

35、 according to the TEDS information, that is according to the specific set of transducer connected in each situation. To fit this in an operational way (velocity and simplicity), we need to include additional information in the system. This information is organized in tables and stored in the FLASH d

36、ata memory of the ADuC and in the external NVRAM. The information of these tables are mostly indexed to point to the different interesting data of each specific channel: TEDS, information of the channel, buffer size and location So, the ADuC software uses these tables basically to access in a simple

37、 and fast way to the TEDS information (also saved in the NVRAM) and to access to the buffers during the measurement and read process. In Fig. 3 we show a block diagram of the STIM software. We have developed different procedures, in assembler, in order to deal with all the possible kind of sensor an

38、d actuator channels defined in the normative. The program can be divided in three parts:1.The initial one is a first-time configuration routine, which stores the basic data from TEDS before the normal working of the STIM (programing of the configuration registers and check-in of the I2C addresses of

39、 the connected modules).2.After that, there is a waiting loop that works in parallel with a periodical interruption routine. This routine scans all the channels defined in the TEDS to perform the periodical actions required in each case.3.And finally, there are three additional blocks of routines, c

40、alled via external interrupts, to perform the answer to.Trigger signal (NTRIG). Communication requests made by the NCAP (NIOE). This includes NCAP sending of channel functions and execution orders.Interrupts generated by the digital channels. Fig. 3. Software block diagram. Most of the procedures wo

41、rk using the information saved in NVRAM and data-Flash. For example, when a trigger to a function channel is invoked via NTRIG, Number of bytes in the channel buffer and Type of channel information in the data-flash is read, and the address of the buffer, TEDS blocks and I2C module address of this c

42、hannel are read from the indexed tables of the NVRAM. The function triggered will be executed using all this information. Fig. 4 shows a block diagram of this process.Fig. 4. Example of utilization of the information saved in memory by the TEDS editor to system work process. One of the particular fu

43、nctions implemented in the software is the “STIM configuration”. This function must be executed at least at the first time that we connect the STIM, and also can be called by the NCAP to update configurations. This function saves the indexed tables and TEDS into the ADuC internal data-flash and into

44、 the NVRAM.Note that when there is any change in the transducers configuration, no firmware update has to be made, only the TEDS and indexed tables have to be modified. Moreover, when the function to update TEDS and tables are invoked, it is not necessary to rewrite the whole TEDS and tables. Instea

45、d, the minimum changes are carried out.If any transducer has been removed, its related data TEDS are removed, and NVRAM is compacted.Any new transducer will add its characteristics to the TEDS.In those situations where there are changes in the characteristics of an existing transducer (new calibrati

46、on for example), the related TEDS are updated.This implies the implementation of algorithms in order to reorganize TEDS information (moving blocks of memory up and down), and to calculate new indexes of the tables. The software is more complicated, but the system is faster and more useful.5. Additio

47、nal tools The key of the IEEE 1451 standard, like in our design, is the structure of TEDS and its inclusion in the STIM. Therefore, an operative system should include effective methods to introduce TEDS information in the STIM. We have developed an additional PC software tool in Delphi. At first, th

48、is tool was thought and used as pseudo-NCAP to test our first STIM.In successive stages of the design, we have enhanced the performances of this tool in order to implement a TEDS editor and the generation of index tables that allows autogeneration of the STIM. The functions and possibilities of the

49、tool are:1.A set of user friendly windows that allows to introduce the transducers characteristics.2.A translator that compiles this information in files in TEDS standard format, as is established by the normative.3.From TEDS, create tables and indexes.4.Save TEDS, tables and indexes into the STIM v

50、ia the standard connector. The first step to start working with the STIM is to configure it. That means to connect it through the PC parallel port and transfer critical classified TEDS information, from files created by the TEDS editor, to the ADuC, as well as the complete TEDS. The ADuC will store

51、them into the different memories of the system in order to have them available during the normal STIM operation.In fact, this tool is the key point of the system. Once it has structured the data in memory, the generic STIM firmware use them in order to manage the transducer set properly.6. Conclusio

52、ns and future works In the present work we have developed an STIM that meets the IEEE 1451 directives and has the capability to work with a lot of different transducers without the necessity of change of the control hardware and software (firmware). In each particular implementation, the user only n

53、eeds to introduce the transducers characteristics (in the way described by the normative) using the TEDS editor. This tool creates the data structure needed and writes it in the STIM.Communication speed between the STIM and NCAP does not depends on the number and type of channels serviced thanks to

54、the software implementation. However, global working speed depends on these parameters due to limited resources of the STIM (one converter multiplexes all the analog input, for example). In order to avoid these situations, more specific modules should be developed with its own converter.Evidently, t

55、his implementation is not the best cost solution in some simple systems, low sampling rates and 1 or 2 channels. But it is a fast and cheap development solution in a lot of situations, because systems developer does not have to work with many kind of hardware and software.Our future work will be foc

56、used in two ways:1.NVRAM is an expensive solution for non-volatile information. Actually we have developed a prototype where we replace the NVRAM by two chips: a FLASH memory for TEDS and indexes of different channels in every section, and a RAM chip for buffers, status and mask registers, and inter

57、mediate buffer to save information in the FLASH memory. This solution is cheaper and powerful because we can increase memory size easily. In Fig. 5 we show a photography of the prototype.Fig. 5. Top side of the new STIM prototype. The FLASH is located in the bottom side.2.Development of an NCAP for Ethernet in order to perform tele-instrumentation with distributed systems within the IEEE 1451 standard in Internet.AcknowledgementsWe acknowledge the support of the CYCIT Spanish investigation project: “Arquitecturas de control distribuido. Anlisis y diseo de estructuras con soporte de tecnol