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1、十五计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITYfiveteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END fiveteencout;ARCHITECTURE counter OF fiveteencout IS SIGNAL count_int:std_logic_vector(0 to 3); BEGINPROCESS(clk,reset
2、)BEGINWAITUNTILrising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1110)THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL;-IF (count_int=1001)THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then -q=0000;-ELSIF(clkevent and clk=1) T
3、HEN-q=q 1;-IF (q=1001)then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAITUNTIL(clkEVENTANDclk = 1);-WAITUNTIL(clockEVENTANDclock = 1);- q=q 1;-endif;-count=q;-WAIT UNTILclock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-clockevent and clock=1;-c
4、ount= 0;-WAITUNTIL(clockEVENTANDclock=1);-WAITriseedge clock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 1;-WAITUNTIL(clockEVENTANDclock=1);-WAITUNTILclock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 2;-endif;-endif;-endif;- END PROCESS; END coun
5、ter;十四计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITYfourteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END fourteencout;ARCHITECTURE counter OF fourteencout IS SIGNAL count_int:std_logic_vector(0 to 3); BEGINPROCESS(clk,r
6、eset)BEGINWAITUNTILrising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1101)THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL;-IF (count_int=1001)THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then -q=0000;-ELSIF(clkevent and clk=
7、1) THEN-q=q 1;-IF (q=1001)then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAITUNTIL(clkEVENTANDclk = 1);-WAITUNTIL(clockEVENTANDclock = 1);- q=q 1;-endif;-count=q;-WAIT UNTILclock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-clockevent and clock=
8、1;-count= 0;-WAITUNTIL(clockEVENTANDclock=1);-WAITriseedge clock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 1;-WAITUNTIL(clockEVENTANDclock=1);-WAITUNTILclock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 2;-endif;-endif;-endif;- END PROCESS; END
9、counter;十三计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITYthireteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END thireteencout;ARCHITECTURE counter OF thireteencout IS SIGNAL count_int:std_logic_vector(0 to 3); BEGINPROCES
10、S(clk,reset)BEGINWAITUNTILrising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1100)THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL;-IF (count_int=1001)THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then -q=0000;-ELSIF(clkevent a
11、nd clk=1) THEN-q=q 1;-IF (q=1001)then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAITUNTIL(clkEVENTANDclk = 1);-WAITUNTIL(clockEVENTANDclock = 1);- q=q 1;-endif;-count=q;-WAIT UNTILclock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-clockevent and
12、 clock=1;-count= 0;-WAITUNTIL(clockEVENTANDclock=1);-WAITriseedge clock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 1;-WAITUNTIL(clockEVENTANDclock=1);-WAITUNTILclock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 2;-endif;-endif;-endif;- END PROCES
13、S; END counter;十二计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITYtwelvecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END twelvecout;ARCHITECTURE counter OF twelvecout IS SIGNAL count_int:std_logic_vector(0 to 3); BEGINPROCESS(
14、clk,reset)BEGINWAITUNTILrising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1011)THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL;-IF (count_int=1001)THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then -q=0000;-ELSIF(clkevent and
15、 clk=1) THEN-q=q 1;-IF (q=1001)then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAITUNTIL(clkEVENTANDclk = 1);-WAITUNTIL(clockEVENTANDclock = 1);- q=q 1;-endif;-count=q;-WAIT UNTILclock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-clockevent and c
16、lock=1;-count= 0;-WAITUNTIL(clockEVENTANDclock=1);-WAITriseedge clock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 1;-WAITUNTIL(clockEVENTANDclock=1);-WAITUNTILclock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 2;-endif;-endif;-endif;- END PROCESS;
17、 END counter;十一计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITYelevencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END elevencout;ARCHITECTURE counter OF elevencout IS SIGNAL count_int:std_logic_vector(0 to 3); BEGINPROCESS(cl
18、k,reset)BEGINWAITUNTILrising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1010)THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL;-IF (count_int=1001)THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then -q=0000;-ELSIF(clkevent and c
19、lk=1) THEN-q=q 1;-IF (q=1001)then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAITUNTIL(clkEVENTANDclk = 1);-WAITUNTIL(clockEVENTANDclock = 1);- q=q 1;-endif;-count=q;-WAIT UNTILclock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-clockevent and clo
20、ck=1;-count= 0;-WAITUNTIL(clockEVENTANDclock=1);-WAITriseedge clock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 1;-WAITUNTIL(clockEVENTANDclock=1);-WAITUNTILclock = 1;-if(clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 2;-endif;-endif;-endif;- END PROCESS; E
21、ND counter;十计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITYcount ISPORT(clk,reset,enable : IN std_logic; count :OUT std_logic_vector(3 downto 0);END count;ARCHITECTURE counter OF count IS SIGNAL count_int:std_logic_vector(0 to 3); BEGINPROCESS(clk,reset)BEGINWAITUN
22、TILrising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1001)THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL;-IF (count_int=1001)THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkeventand clk=1) THEN-q=q 1;-IF
23、(q=1001)then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAITUNTIL(clkEVENTANDclk = 1);-WAITUNTIL(clockEVENTANDclock = 1);- q=q 1; -end if; -count=q;- WAIT UNTIL clock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-clockevent and clock=1;-count= 0;
24、-WAITUNTIL(clockEVENTANDclock=1);-WAITriseedge clock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 1;-WAITUNTIL(clockEVENTANDclock=1);-WAITUNTILclock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 2;-endif;-endif;-endif;- END PROCESS; END counter;九计
25、数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITYninecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END ninecout;ARCHITECTURE counter OF ninecout IS SIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAITUNTILr
26、ising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1000)THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL;-IF (count_int=1001)THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkeventand clk=1) THEN-q=q 1;-IF (q=1
27、001)then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAITUNTIL(clkEVENTANDclk = 1);-WAITUNTIL(clockEVENTANDclock = 1);- q=q 1; -end if; -count=q;- WAIT UNTIL clock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-clockevent and clock=1;-count= 0;-WAI
28、TUNTIL(clockEVENTANDclock=1);-WAITriseedge clock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 1;-WAITUNTIL(clockEVENTANDclock=1);-WAITUNTILclock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 2;-endif;-endif;-endif;- END PROCESS; END counter;八计数器li
29、brary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITYeightcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(2 downto 0);END eightcout;ARCHITECTURE counter OF eightcout IS SIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAITUNTILri
30、sing_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=111)THENcount_int=000;ELSEcount_int = count_int 1;-ELSE- NULL;-IF (count_int=1001)THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkeventand clk=1) THEN-q=q 1;-IF (q=1001
31、)then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAITUNTIL(clkEVENTANDclk = 1);-WAITUNTIL(clockEVENTANDclock = 1);- q=q 1; -end if; -count=q;- WAIT UNTIL clock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-clockevent and clock=1;-count= 0;-WAITUN
32、TIL(clockEVENTANDclock=1);-WAITriseedge clock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 1;-WAITUNTIL(clockEVENTANDclock=1);-WAITUNTILclock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 2;-endif;-endif;-endif;- END PROCESS; END counter;六计数器libra
33、ry ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITYsixcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(2 downto 0);END sixcout;ARCHITECTURE counter OF sixcout IS SIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAITUNTILrising_edge
34、(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=101)THENcount_int=000;ELSEcount_int = count_int 1;-ELSE- NULL;-IF (count_int=1001)THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then -q=0000;-ELSIF(clkevent and clk=1) THEN -q=q 1;-IF (q=1001) then
35、 -q=0000;-END IF;-IF (reset=1)THEN -q=00;-ELSIF-wait until (clkevent and clk=1);-WAITUNTIL(clkEVENTANDclk = 1);-WAITUNTIL(clockEVENTANDclock = 1);- q=q 1; -end if; -count=q;- WAIT UNTIL clock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-clockevent and clock=1;-count= 0;-WAITUNTIL(clockEVENTANDclock=1);-WAITriseedge clock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 1;-WAITUNTIL(clockEVENTANDclock=1);-WAITUNTILclock = 1;-if (clockeventand clock=1)then-WAITUNTILrising_edge(clock);-count= 2;-end if;-end if;-end if;- END PROCESS; END counter;
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