外文翻译基于单片机的步进电机电路控制设计

1、淮 阴 工 学 院毕业设计(论文)外文翻译学 生 姓 名：赵 辉学 号：3082107138专 业：电子信息工程设计(论文)题目：基于单片机的步进电机控制电路设计指 导 教 师:庄 立 运 2012年 4 月 10日基于单片机的步进电机电路控制设计 89c51是一种带4k字节闪烁可编程可擦除只读存储器（fperomfalsh programmable and erasable read only memory）的低电压、高性能cmos8位微处理器，俗称单片机。该器件采用atmel高密度非易失存储器制造技术制造，与工业标准的mcs-51指令集和输出管脚相兼容。由于将多功能8位cpu和闪烁存储器组

2、合在单个芯片中，atmel的89c51是一种高效微控制器，89c2051是它的一种精简版本。89c单片机为很多嵌入式控制系统提供了一种灵活性高且价廉的方案。功能特点·与mcs-51 兼容 ·4k字节可编程闪烁存储器 · 寿命：1000写/擦循环 ·数据保留时间：10年 ·全静态工作：0hz-24mhz ·三级程序存储器锁定 ·128*8位内部ram ·32可编程i/o线 ·两个16位定时器/计数器 ·5个中断源 ·可编程串行通道 ·低功耗的闲置和掉电模式 ·片内振荡

3、器和时钟电路管脚说明vcc：供电电压。 gnd：接地。 p0口：p0口为一个8位漏级开路双向i/o口，每脚可吸收8ttl门电流。当p1口的管脚第一次写1时，被定义为高阻输入。p0能够用于外部程序数据存储器，它可以被定义为数据/地址的低八位。在fiash编程时，p0 口作为原码输入口，当fiash进行校验时，p0输出原码，此时p0外部必须被拉高。 p1口：p1口是一个内部提供上拉电阻的8位双向i/o口，p1口缓冲器能接收输出4ttl门电流。p1口管脚写入1后，被内部上拉为高，可用作输入，p1口被外部下拉为低电平时，将输出电流，这是由于内部上拉的缘故。在flash编程和校验时，p1口作为第八位地址

4、接收。 p2口：p2口为一个内部上拉电阻的8位双向i/o口，p2口缓冲器可接收，输出4个ttl门电流，当p2口被写“1”时，其管脚被内部上拉电阻拉高，且作为输入。并因此作为输入时，p2口的管脚被外部拉低，将输出电流。这是由于内部上拉的缘故。p2口当用于外部程序存储器或16位地址外部数据存储器进行存取时，p2口输出地址的高八位。在给出地址“1”时，它利用内部上拉优势，当对外部八位地址数据存储器进行读写时，p2口输出其特殊功能寄存器的内容。p2口在flash编程和校验时接收高八位地址信号和控制信号。 p3口：p3口管脚是8个带内部上拉电阻的双向i/o口，可接收输出4个ttl门电流。当p3口写入“1

5、”后，它们被内部上拉为高电平，并用作输入。作为输入，由于外部下拉为低电平，p3口将输出电流（ill）这是由于上拉的缘故。p3口也可作为at89c51的一些特殊功能口. 口管脚 备选功能 p3.0 rxd（串行输入口） p3.1 txd（串行输出口） p3.2 /int0（外部中断0） p3.3 /int1（外部中断1） p3.4 t0（记时器0外部输入） p3.5 t1（记时器1外部输入） p3.6 /wr（外部数据存储器写选通） p3.7 /rd（外部数据存储器读选通） p3口同时为闪烁编程和编程校验接收一些控制信号。 rst：复位输入。当振荡器复位器件时，要保持rst脚两个机器周期的高电平

6、时间。ale/prog：当访问外部存储器时，地址锁存允许的输出电平用于锁存地址的地位字节。在flash编程期间，此引脚用于输入编程脉冲。在平时，ale端以不变的频率周期输出正脉冲信号，此频率为振荡器频率的1/6。因此它可用作对外部输出的脉冲或用于定时目的。然而要注意的是：每当用作外部数据存储器时，将跳过一个ale脉冲。如想禁止ale的输出可在sfr8eh地址上置0。此时， ale只有在执行movx，movc指令是ale才起作用。另外，该引脚被略微拉高。如果微处理器在外部执行状态ale禁止，置位无效。 /psen：外部程序存储器的选通信号。在由外部程序存储器取指期间，每个机器周期两次/psen有

7、效。但在访问外部数据存储器时，这两次有效的/psen信号将不出现。 /ea/vpp：当/ea保持低电平时，则在此期间外部程序存储器（0000h-ffffh），不管是否有内部程序存储器。注意加密方式1时，/ea将内部锁定为reset；当/ea端保持高电平时，此间内部程序存储器。在flash编程期间，此引脚也用于施加12v编程电源（vpp）。 xtal1：反向振荡放大器的输入及内部时钟工作电路的输入。 xtal2：来自反向振荡器的输出。振荡器特性xtal1和xtal2分别为反向放大器的输入和输出。该反向放大器可以配置为片内振荡器。石晶振荡和陶瓷振荡均可采用。如采用外部时钟源驱动器件，xtal2应不

8、接。由于输入至内部时钟信号要通过一个二分频触发器，因此对外部时钟信号的脉宽无任何要求，但必须保证脉冲的高低电平要求的宽度。figure 1. oscillator connections figure 2. external clock drive芯片擦除整个perom阵列和三个锁定位的电擦除可通过正确的控制信号组合，并保持ale管脚处于低电平10ms 来完成。在芯片擦操作中，代码阵列全被写“1”且在任何非空存储字节被重复编程以前，该操作必须被执行。 此外，at89c51设有稳态逻辑，可以在低到零频率的条件下静态逻辑，支持两种软件可选的掉电模式。在闲置模式下，cpu停止工作。但ram，定时器，

9、计数器，串口和中断系统仍在工作。在掉电模式下，保存ram的内容并且冻结振荡器，禁止所用其他芯片功能，直到下一个硬件复位为止。空闲模式在空闲模式下,中央处理器把自己睡;所有的微外设保持活跃。该模式调用的软件。片上的内容的公绵羊、所有的特殊功能寄存器不变在这个模式下。空闲模式可以终止任何使中断或由硬件复位。应该指出的是,闲时终止一个硬件复位,设备通常程序执行,从简历在它停止两封,机器周期之前,内部重置算法以控制。样品的硬件抑制进入内部ram在这种情况下,但进入港口大头针空洞。消除这种可能性一个出乎意料的写信给一个港口销闲时被终止,由复位、指导证明那个中调用一个空闲不应该写端口销或外部存储器。pow

10、er-down模式在power-down模式下,振子是结束了,但这个指令;用它召唤“power-down是最后的指令执行。这片上的公绵羊、特殊功能寄存器值,直到power-down保留自己的方式终止。唯一的退出,是一家五金power-down重置。sfrs重置重新定义,但不改变样品的公羊。重置不应该被激活之前vcc回到正常操作水平,都必须保持活跃的时间还不够久,允许振荡器来重新启动和稳定。程序记忆锁位在芯片上的三个锁位可以离开unprogrammed(u)或可编程(p)获得的额外功能列在下表。当锁点,1是程序逻辑电平ea销样品并就搭在重置。如果这个装置是开机没有重置,门闩初始化一个随机值,认为

11、直到重置价值被激活。加入是必要的值ea是一致的逻辑与当前水平销为设备正常运作步进电机介绍步进电机是将数字脉冲输入转换为模拟角度输出的电磁增量运动装置。其内在的步进能力允许没有反馈的精确位置控制。 也就是说，他们可以在开环模式下跟踪任何步阶位置，因此执行位置控制是不需要任何反馈的。步进电机提供比直流电机每单位更高的峰值扭矩;此外，它们是无电刷电机，因此需要较少的维护。所有这些特性使得步进电机在许多位置和速度控制系统的选择中非常具有吸引力，例如如在计算机硬盘驱动器和打印机，代理表，机器人中的应用等.尽管步进电机有许多突出的特性，他们仍遭受振荡或不稳定现象。这种现象严重地限制其开环的动态性能和需要高

12、速运作的适用领域。 这种振荡通常在步进率低于1000脉冲/秒的时候发生，并已被确认为中频不稳定或局部不稳定1，或者动态不稳定2。此外，步进电机还有另一种不稳定现象，也就是在步进率较高时，即使负荷扭矩小于其牵出扭矩，电动机也常常不同步。该文中将这种现象确定为高频不稳定性，因为它以比在中频振荡现象中发生的频率更高的频率出现。高频不稳定性不像中频不稳定性那样被广泛接受，而且还没有一个方法来评估它。中频振荡已经被广泛地认识了很长一段时间，但是，一个完整的了解还没有牢固确立。这可以归因于支配振荡现象的非线性是相当困难处理的。大多数研究人员在线性模型基础上分析它1。尽管在许多情况下，这种处理方法是有效的或

13、有益的，但为了更好地描述这一复杂的现象，在非线性理论基础上的处理方法也是需要的。例如，基于线性模型只能看到电动机在某些供应频率下转向局部不稳定，并不能使被观测的振荡现象更多深入。事实上，除非有人利用非线性理论，否则振荡不能评估。窗体顶端窗体底端因此，在非线性动力学上利用被发展的数学理论处理振荡或不稳定是很重要的。值得指出的是，taft和gauthier3，还有taft和harned4使用的诸如在振荡和不稳定现象的分析中的极限环和分界线之类的数学概念，并取得了关于所谓非同步现象的一些非常有启发性的见解。尽管如此，在这项研究中仍然缺乏一个全面的数学分析。本文一种新的数学分被开发了用于分析步进电机的

14、振动和不稳定性。本文的第一部分讨论了步进电机的稳定性分析。结果表明，中频振荡可定性为一种非线性系统的分叉现象（霍普夫分叉）。本文的贡献之一是将中频振荡与霍普夫分叉联系起来，从而霍普夫理论从理论上证明了振荡的存在性。高频不稳定性也被详细讨论了，并介绍了一种新型的量来评估高频稳定。这个量是很容易计算的，而且可以作为一种标准来预测高频不稳定性的发生。在一个真实电动机上的实验结果显示了该分析工具的有效性。本文的第二部分通过反馈讨论了步进电机的稳定性控制。一些设计者已表明，通过调节供应频率 5 ，中频不稳定性可以得到改善。特别是pickup和russell 6，7都在频率调制的方法上提出了详细的分析。在

15、他们的分析中，雅可比级数用于解决常微分方程和一组数值有待解决的非线性代数方程组。此外，他们的分析负责的是双相电动机，因此，他们的结论不能直接适用于我们需要考虑三相电动机的情况。在这里，我们提供一个没有必要处理任何复杂数学的更简洁的稳定步进电机的分析。在这种分析中，使用的是d-q模型的步进电机。由于双相电动机和三相电动机具有相同的d-q模型，因此，这种分析对双相电动机和三相电动机都有效。迄今为止，人们仅仅认识到用调制方法来抑制中频振荡。本文结果表明，该方法不仅对改善中频稳定性有效，而且对改善高频稳定性也有效。动态模型的步进电机本文件中所考虑的步进电机由一个双相或三相绕组的跳动定子和永磁转子组成。

16、一个极对三相电动机的简化原理如图1所示。步进电机通常是由被脉冲序列控制产生矩形波电压的电压源型逆变器供给的。这种电动机用本质上和同步电动机相同的原则进行作业。步进电机主要作业方式之一是保持提供电压的恒定以及脉冲频率在非常广泛的范围上变化。在这样的操作条件下，振动和不稳定的问题通常会出现。图1.三相电动机的图解模型 用qd框架参考转换建立了一个三相步进电机的数学模型 。下面给出了三相绕组电压方程va = ria + l*dia /dt m*dib/dt m*dic/dt + dpma/dt ,vb = rib + l*dib/dt m*dia/dt m*dic/dt + dpmb/dt ,vc

17、= ric + l*dic/dt m*dia/dt m*dib/dt + dpmc/dt , (1) 其中r和l分别是相绕组的电阻和感应线圈，并且m是相绕组之间的互感线圈。pma, pmb and pmc 是应归于永磁体 的相的磁通，且可以假定为转子位置的正弦函数如下pma = 1 sin(n),pmb = 1 sin(n 2 /3),pmc = 1 sin(n - 2 /3), (2)其中n是转子齿数。本文中强调的非线性由上述方程所代表，即磁通是转子位置的非线性函数。使用q ,d转换，将参考框架由固定相轴变换成随转子移动的轴（参见图2）。矩阵从a,b,c框架转换成q,d框架变换被给出了8 (

18、3)例如，给出了q,d参考里的电压 (4)在a,b,c参考中，只有两个变量是独立的（ia + ib + ic = 0），因此，上面提到的由三个变量转化为两个变量是允许的。在电压方程（1）中应用上述转换，在q,d框架中获得转换后的电压方程为vq = riq + l1*diq/dt + nl1id + n1,vd = rid + l1*did/dt nl1iq, (5) 图2，a,b,c和d,q参考框架其中l1 = l + m，且是电动机的速度。有证据表明,电动机的扭矩有以下公式t = 3/2n1iq . (6)转子电动机的方程为j*d/dt = 3/2*n1iq bf tl , (7) 如果bf

19、是粘性摩擦系数，和tl代表负荷扭矩（在本文中假定为恒定）。为了构成完整的电动机的状态方程，我们需要另一种代表转子位置的状态变量。为此，通常使用满足下列方程的所谓的负荷角8d/dt = 0 , (8) 其中0是电动机的稳态转速。方程（5），（7），和（8）构成电动机的状态空间模型，其输入变量是电压vq和vd.如前所述，步进电机由逆变器供给，其输出电压不是正弦电波而是方波。然而，由于相比正弦情况下非正弦电压不能很大程度地改变振荡特性和不稳定性（如将在第3部分显示的，振荡是由于电动机的非线性），为了本文的目的我们可以假设供给电压是正弦波。根据这一假设，我们可以得到如下的vq和vdvq = vmcos

20、(n) ,vd = vmsin(n) , (9) 其中vm是正弦波的最大值。上述方程，我们已经将输入电压由时间函数转变为状态函数，并且以这种方式我们可以用自控系统描绘出电动机的动态，如下所示。这将有助于简化数学分析。根据方程（5），（7），和（8），电动机的状态空间模型可以如下写成矩阵式 = f(x,u) = ax + fn(x) + bu , (10) 其中x = iq id t, u = 1 tl t 定义为输入，且1 = n0 是供应频率。输入矩阵b被定义为矩阵a是f(.)的线性部分，如下fn(x)代表了f(.)的线性部分，如下输入端u独立于时间，因此，方程（10）是独立的。在f(x,u

21、)中有三个参数，它们是供应频率1，电源电压幅度vm和负荷扭矩tl。这些参数影响步进电机的运行情况。在实践中，通常用这样一种方式来驱动步进电机，即用因指令脉冲而变化的供应频率1来控制电动机的速度，而电源电压保持不变。因此，我们应研究参数1的影响。3.分叉和中频振荡，设=0，得出方程（10）的平衡且是它的相角， = arctan(1l1/r) . (16) 方程（12）和（13）显示存在着多重均衡，这意味着这些平衡永远不能全局稳定。人们可以看到，如方程（12）和（13）所示有两组平衡。第一组由方程（12）对应电动机的实际运行情况来代表。第二组由方程（13）总是不稳定且不涉及到实际运作情况来代表。在

22、下面，我们将集中精力在由方程（12）代表的平衡上。附件2：外文原文 the stepper motor control circuit be based on single chip microcomputerthe at89c51 is a low-power, high-performance cmos 8-bit microcomputer with 4k bytes of flash programmable and erasable read only memory (perom). the device is manufactured using atmels high-densi

23、ty nonvolatile memory technology and is compatible with the industry-standard mcs-51 instruction set and pinout. the on-chip flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. by combining a versatile 8-bit cpu with flash on a monolithic

24、chip, the atmel at89c51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.function characteristicthe at89c51 provides the following standard features: 4k bytes of flash, 128 bytes of ram, 32 i/o lines, two 16-bit timer/coun

25、ters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. in addition, the at89c51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu wh

26、ile allowing the ram, timer/counters, serial port and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator disabling all other chip functions until the next hardware reset.pin descriptionvcc：supply voltage.gnd：ground.port 0：port 0 is an 8-bi

27、t open-drain bi-directional i/o port. as an output port, each pin can sink eight ttl inputs. when 1s are written to port 0 pins, the pins can be used as highimpedance inputs.port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data mem

28、ory. in this mode p0 has internal pullups.port 0 also receives the code bytes during flash programming,and outputs the code bytes during programverification. external pullups are required during programverification.port 1port 1 is an 8-bit bi-directional i/o port with internal pullups.the port 1 out

29、put buffers can sink/source four ttl inputs.when 1s are written to port 1 pins they are pulled high by the internal pullups and can be used as inputs. as inputs,port 1 pins that are externally being pulled low will source current (iil) because of the internal pullups.port 1 also receives the low-ord

30、er address bytes during flash programming and verification.port 2port 2 is an 8-bit bi-directional i/o port with internal pullups.the port 2 output buffers can sink/source four ttl inputs.when 1s are written to port 2 pins they are pulled high by the internal pullups and can be used as inputs. as in

31、puts,port 2 pins that are externally being pulled low will source current, because of the internal pullups.port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. in this application, it uses strong i

32、nternal pullupswhen emitting 1s. during accesses to external data memory that use 8-bit addresses, port 2 emits the contents of the p2 special function register.port 2 also receives the high-order address bits and some control signals during flash programming and verification.port 3port 3 is an 8-bi

33、t bi-directional i/o port with internal pullups.the port 3 output buffers can sink/source four ttl inputs.when 1s are written to port 3 pins they are pulled high by the internal pullups and can be used as inputs. as inputs,port 3 pins that are externally being pulled low will source current (iil) be

34、cause of the pullups.port 3 also serves the functions of various special features of the at89c51 as listed below:port 3 also receives some control signals for flash programming and verification.rstreset input. a high on this pin for two machine cycles while the oscillator is running resets the devic

35、e.ale/progaddress latch enable output pulse for latching the low byte of the address during accesses to external memory. this pin is also the program pulse input (prog) during flash programming.in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for

36、 external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory.if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is

37、 weakly pulled high. setting the ale-disable bit has no effect if the microcontroller is in external execution mode.psenprogram store enable is the read strobe to external program memory.when the at89c51 is executing code from external program memory, psen is activated twice each machine cycle, exce

38、pt that two psen activations are skipped during each access to external data memory.ea/vppexternal access enable. ea must be strapped to gnd in order to enable the device to fetch code from external program memory locations starting at 0000h up to ffffh. note, however, that if lock bit 1 is programm

39、ed, ea will be internally latched on reset.ea should be strapped to vcc for internal program executions.this pin also receives the 12-volt programming enable voltage(vpp) during flash programming, for parts that require12-volt vpp.xtal1input to the inverting oscillator amplifier and input to the int

40、ernal clock operating circuit.xtal2output from the inverting oscillator amplifier.oscillator characteristicsxtal1 and xtal2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 1.either a quartz crystal or ceram

41、ic resonator may be used. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 2.there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by

42、-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. figure 1. oscillator connections figure 2. external clock drive configurationidle modein idle mode, the cpu puts itself to sleep while all the onchip peripherals remain active. the mode is invoked by s

43、oftware. the content of the on-chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset.it should be noted that when idle is terminated by a hard ware reset, the device normally resumes program

44、 execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is

45、terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory.power-down modein the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. the on-chip ram a

46、nd special function registers retain their values until the power-down mode is terminated. the only exit from power-down is a hardware reset. reset redefines the sfrs but does not change the on-chip ram. the reset should not be activated before vcc is restored to its normal operating level and must

47、be held active long enough to allow the oscillator to restart and stabilize.program memory lock bitson the chip are three lock bits which can be left unprogrammed (u) or can be programmed (p) to obtain the additional features listed in the table below.when lock bit 1 is programmed, the logic level a

48、t the ea pin is sampled and latched during reset. if the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. it is necessary that the latched value of ea be in agreement with the current logic level at that pin in order for th

49、e device to function properly.introductionstepper motors are electromagnetic incremental-motion devices which convert digital pulse inputs to analog angle outputs. their inherent stepping ability allows for accurate position control without feedback. that is, they can track any step position in open

50、-loop mode, consequently no feedback is needed to implement position control. stepper motors deliver higher peak torque per unit weight than dc motors; in addition, they are brushless machines and therefore require less maintenance. all of these properties have made stepper motors a very attractive

51、selection in many position and speed control systems, such as in computer hard disk drivers and printers, xy-tables, robot manipulators, etc.although stepper motors have many salient properties, they suffer from an oscillation or unstable phenomenon. this phenomenon severely restricts their open-loo

52、p dynamic performance and applicable area where high speed operation is needed. the oscillation usually occurs at stepping rates lower than 1000 pulse/s, and has been recognized as a mid-frequency instability or local instability 1, or a dynamic instability 2. in addition, there is another kind of u

53、nstable phenomenon in stepper motors, that is, the motors usually lose synchronism at higher stepping rates, even though load torque is less than their pull-out torque. this phenomenon is identified as high-frequency instability in this paper, because it appears at much higher frequencies than the f

54、requencies at which the mid-frequency oscillation occurs. the high-frequency instability has not been recognized as widely as mid-frequency instability, and there is not yet a method to evaluate it.mid-frequency oscillation has been recognized widely for a very long time, however, a complete underst

55、anding of it has not been well established. this can be attributed to the nonlinearity that dominates the oscillation phenomenon and is quite difficult to deal with.384 l. cao and h. m. schwartzmost researchers have analyzed it based on a linearized model 1. although in many cases, this kind of trea

56、tments is valid or useful, a treatment based on nonlinear theory is needed in order to give a better description on this complex phenomenon. for example, based on a linearized model one can only see that the motors turn to be locally unstable at some supplyfrequencies, which does not give much insight into the observed oscillatory phenomenon. in fact, the oscillation cannot be assessed unless one uses nonlinear theory.therefore, it is significant to use developed mathematical theory on nonlinear dynamics to handle the oscillation or instability. it