课程设计论文-基于VHDL语言的流水灯设计

1、步2佇g八滨江学院课程论文（可编程器件原理与应用）题目基丁 vhdl 语言的流水灯设计学生姓名学号院系滨江学院专业电子与信息工程指导教师二零一零年十二月三十口采用altera公司的epm7128slc84-10芯片，通过vhdl语言设 计一个流水灯电路。流水灯样式必须大于3种，且可以通过按键调节 显示样式；可以通过按键调节流水灯变化快慢；当前流水灯样式和变 化速度能够通过数码管显示出来；（附加：具有按键声）二、设计框图（框图说明）速度按键样式按键译码和扫描1000hz信号蜂鸣器控制模块100hz信号数码显示a速度控制一样式选择 彩灯显示1mhz周期信号经过2个100分频，得到100hz，再经过

2、1个10 分频得到10hz信号，传给速度控制模块，得到需要的速度周期信号, 然后传给样式选择模块，样式选择模块直接输出彩灯样式；控制模块 通过接受两个按键信号，同时控制速度控制模块和样式选择模块；译 码扫描模块通过判断控制模块，扫描数码管显示当前彩灯样式和彩灯 变化速度；按键信号通过延时模块输出按键发生信号。三、原理图（cpld内部原理说明）shoc从原理图中可以看到，一共有8种模块，d触发器的作用是对按钮进行消抖，除d触发器之外的7个模块功能及作用如下：fl00和 flo分别是100和10的分频器，speed模块的作用是对彩灯变化速度 进行控制，而style_switch模块的作用是对彩灯样

3、式进行调节。control 模块接收按键信号对样式和速度进行总的控制。show模块是对速度 值和样式值进行译码并进行扫描数码管，将当前样式和速度状态显示 出来。deby模块则是对按键声的延时。1.h00模块功能：100分频波形仿真：vhdl代码:iibrary ieee;use i eee std_iogi c_1164. all;use i eee std_iog i c_uns i gned. all;ent i ty f 100 i s -100 分频port(elk:in std_logic;sec:out std_logic);end entity f100;arch itectur

4、e getsec of f 100 i ss i gnal secout : std_logic : = ,1' beginprocess (cik) i svariable count100:integer range 0 to 50;begi nif elk1event and cik=11' thencountl00:=count100+1;i f countl00=50 then secout二not secout; count100:=0;end i f;end if;end process; sec<=secout;end architecture getse

5、c;2. f10模块功能：10分频波形仿真:u elkjl1wwirln_n_n_n_n_mwurarltlsec010.0ms20.0ms30.0ms40.0msname:value:vhdl代码：ii brary ieee;use i eee. std_iog i c_1164. a i i;use i eee std_iogi c_uns i gned. all;entity f 10 is 10 分频 port(elk:in std_logic;sec:out std_logic);end entity f10;arch itecture getsec of f10 i ss i gn

6、ai secout : std_logic : = '11; beginprocess (cik) i svariable count10:integer range 0 to 5;beginif elk1event and cik=11' thencount10:=count10+1;i f countio二5 thensecout二not secout; counts0:=0;end if;end if;end process; sec<=secout;end architecture getsec;3. speed 模块功能：根据date输入端的数值大小，产生不同频

7、率的周期 信号，从而达到控制彩灯变化速率的目的。波形仿真：name:value:10.0ms20 oms130.0ms40 0ms150 0ms60.0ms1clr0uh elk01datehoh n l o h ： h1 )( 2xj_lspd_out1lvhdl代码：ii brary ieee;use i eee std_iog i c_1164. a i i;use i eee std_iogi c_uns i gned. all;ent i ty speed i s -速度控制 port(cik,cir:in std_logic;date:in std_logic_vector (1

8、downto 0); spd_out:out std_logic);end entity speed;architecture arch of speed i ss i gna i spd_num: std_ i og i c_vector (1 down to 0) =00"s i gna i num: std_i og i c_vector (1 downto 0)=00"s i gnai out_temp : std_logic = (t ;beginprocess (c i kt c i r) i s beginspd_num 二 3-date;if cir=

9、9;1' then num <= "00"spd_num <= 3-date; out_temp u 01 ;seif elk1event and cik='1' theni f num>=spd_num then numuoo”；out_temp<=not out_temp;e i senum<=num+1;end i f;end if;end if;end process;spd_out二out_temp;end architecture arch;4. sty le_switch 模块功能：根据date输入端的数值

10、大小，输出不同的彩灯样式波形仿真:name:value: r15.0ms20.0ms25.0ms30 0msi clr3c0elk0dateh2style_outh 7fffx6db6 x36db x5b6d 6db6 36db x 5b6d x6db6 36db x 5b6d x6db6 36dvhdl代码:ii brary ieee;use i eee. std_iog i c_1164.all;use i eee. std_iogi c_uns i gned. all;entity sty le_switch i s -样式选择port(elk,clr:in std_logic;date

11、:in std_logic_vector (1 downto 0);style_out:out std_iog i c_vector (14 downto 0); end entity style_switch;architecture arch of style_switch i ss i gnai style_num:std_logic_vector(1 downto 0); s i gnai sty ie_over:std_log i c: = 'o'beginprocess (c i k, c i r) i svar iable temp: integer range

12、0 to 7;beg ini f ci11 thentemp:二0;style_num <= "00" e i sei f elk1event andcik=,1' thenif date二"00" theni f sty le_over二 then sty ie_num<=styie_num+1; end if ;sty ie_num<=date;end if;case style_num i swhen ”00"=>case temp i swhen 0 二sty i e_out<=,000000000

13、000000,*;when 1=> sty i e_out <=n111111111111111;when 2=> sty ie_out <="000000000000000"when 3二sty ie_out <=n111111111111111"when others => style_out <=n111111111111111h; end case;temp:二temp+1;i f temp>3 then style_over<=, 1 temp:=0;e i sestyle_over<='

14、;0 ;end if;when or1 =>case temp i swhen 0 => sty i e_out<=11000000000000000n ;when仁sty i e_out二 7门门 0000000000”;when 2=> style_outwhen 3二style_outwhen 4二style_out<=,0000011111111ir,;when 5二style_out<=,l000000000011111when others => sty ie_out <=n111111111111111end case;temp:二

15、temp+1;i f temp>5 then sty ie_over<=,11;temp:二0;e i sestyle_over<='0' end if;when h10u=>when 0> sty ie_outwhen 1> style_outwhen 2> sty ie_outwhen 3> style_outwhen 4> sty ie_outwhen 5> sty ie_outwhen others =>sty iend case;case temp i s<=f, 100100100100100h

16、;<=n010010010010010n;<="001001001001001<=* 100100100100100n;<=n010010010010010n;<=,ooiooiooiooioor,；_out1111111h;temp:二temp+1 ;if temp>5 then style_over<='1 temp:=0;e i sestyle_over<='0r ; end if;when h11n=>case temp i swhen 0whe n 1when 2when 3when 4when 5>

17、; style_out> style_out> style_out> sty ie_out> sty ie_out> sty ie_out<=n000000000000000n <=n111000000000111° <=n111111000111111'* <=*111111111111111" <="111111000111111" <=h111000000000111mwhen others => sty ie_out <=h111111111111111end

18、case;temp:二temp+1; if temp>5 then sty i e_overu 1 temp:=0;e i sestyle_over<='0f ;end if;when others 二style_out <=h111111111111111 end case;end if;end if;end process;end architecture arch;5. control 模块功能：接收按键信号，调节彩灯样式和变化速度值波形仿真:value:,l5.0msi10.0msi15.0msiol0jh 1dc1 :!：2 )*3)0h 10-jlj20n

19、ame】n key_speed speed_out key_style style_outvhdl代码：ii brary ieee;use i eee. std_iog i c_1164. a i i;use i eee std_iogi c_uns i gned. all;entity control is -控制模块port (key_speedt key_style: in std_logic;speed_out. style_out:out std_logic_vector (1 downto 0); end entity control;architecture arch of co

20、ntrol iss i gnai speed_num:std_iog i c_vector (1 downto 0);s i gnai sty ie_num:std_iog i c_vector (1 downto 0);beginprocess (key_speed) i sbegi ni f key_speedf everrt and key_speed=, 1 ' thenspeed_num二speed_num+1;end if;end process;process (key_styie) i s beginif key_style'event and key_styi

21、e=,1' thensty ie_num<=styie_num+1;end i f ;end process;speed_out二speed_num;sty ie_out二sty ie_num;end architecture arch;6. show模块功能：译码和数码管的动态扫描波形仿真:value:0h 0h 0h 3fh 110.0ms15.0ms20.0ms25.0m$name:cik style speed duan weivhdl代码：ii brary i eee;use i eee std_iogi c_1164. all;use i eee std_iog i

22、c_uns i gned all;entity show i s -译码和数码管显示port(elk:in std_logic;style,speed:in std_logic_vector (1 downto 0); duan:out std_logic_vector (6 downto 0);we i:out std_logic_vector (1 downto 0); end entity show;architecture arch of show i sbeginprocess (cik) i svar iabie temp: integer range 0 to 1; begini

23、f elk1event and cik='1' thenif temp =0 then sty ie i s=>二二 =>casewhen when when whe n when”00”or*nnnduan<=n01111ir,;duan<=,0000110"duan<=,1011011n;duan<=h1001111"others 二duan<=h1111111"end case; wei<=h10"casewhenwhen when whe nwhenspeed i s二=>二二

24、“oct”01”“10” ” iiduan<=,01111ir,;dua* 二“0000110“；duan<="1011011" duan<=,1001111n;others => duan<="1111111"end case; weiuor;end if; temp:=temp+1 ;end if;end process;end architecture arch;7. delay 模块功能：按键按下之后，蜂鸣器鸣叫延时波形仿真：name:valuer r5.0 ms10.015.0ms20.0ms25conol0elk

25、0ld out0vhdl代码:ii brary i eee;use i eee std_iogi c_1164. all; use i eee std_iog i c_uns i gned all;entity de i ay i s -蜂鸣器延时 port(cikr con:in std_logic;d_out:out std_logic);end entity delay;architecture arch of de i ay i ss i gna i num: std_i ogi c_vector (1 downto 0)='00" beginprocess (c i

26、 k, con) i sbegi ni f con二1' thennum<=,0r,;d out<='1'if elk1event and cik=,11 theni f num/=,00" thennum二num-1;e i sed outuo'end i f;end if;end if;end process;end architecture arch;五、结果为验证所设计程序是否正确，将程序下载进行硬件测试。在 max+plus n开发环境中进行管脚锁定，连接好下载线，然后将目 标文件下载到器件中。经过测试，流水灯样式一共有4种，第0种样式为样式1、2、3 的综合，且可以通过按键调节显示样式；通过按键能够调节流水灯变 化快慢，速度0为最慢速度，而速度3为最快速度；当前流水灯样式 和变化速度也能够通过数码管显示出来；同时为了突出按键效果，按 键被按下时，蜂鸣器能够发出鸣叫声。