用Verilog做的SD卡控制器有详细的注释

1、用Verilog 做的SD卡控制器-SD 卡-II 2011-12-02 15:53/SD命令CMDS送控制/1.发送8个时钟脉冲/ 2. SD 卡片选CSS低，即片选有效/ 3. 连续发送6个字节命令/ 4. 接收1个字节响应数据/ 5. SD 卡片选CS拉高，即关闭SDK/*发送总共6个字节命令格式：0 - start bit1 - hostbit5-0 - commandbit31-0 - argumentbit6-0 - CRC71 - end bit*/发送sd命令状态机控制reg5:0 cmd;/发送命令寄存器reg31:0 arg;/发送参数寄存器reg7:0 crc;/ 发送

2、CRCK验码reg spi_cs_nr;/SPI 从设备使能信号，由主设备控制reg spi_tx_enr;/SPI 数据发送使能信号，高有效reg spi_rx_enr;/SPI 数据接收使能信号，高有效reg7:0 spi_tx_dbr;/SPI 数据发送寄存器reg7:0 spi_rx_dbr;/SPI 数据接收寄存器reg3:0 nclk_cnt;/74+CLK发送周期计数器reg7:0 wait_cnt8;/命令操作间隔等待计数器reg9:0 cnt512;/ 读取 512B 计数器reg7:0 retry_rep;/重复读取 respone 计数器reg7:0 retry_cmd;

3、/重复当前命令计数器assign spi_cs_n = spi_cs_nr;assign spi_tx_en = spi_tx_enr;assign spi_rx_en = spi_rx_enr;assign spi_tx_db = spi_tx_dbr;assign sd_dout = spi_rx_dbr;/每接收一个字节数据，该位置高一个时钟周期，共 512Bassign sd_fifowr = (spi_rx_rdy & spi_rx_enr & (cmd_cstate = CMD_RD) & (cnt512 < 10'd513);wire cmd

4、_clk = (sdinit_cstate = SDINIT_CLK);/ 进入上电初始化时的 74+CLK 产生状态标志位wire cmd_en = (sdinit_cstate = SDINIT_CMD0) | (sdinit_cstate = SDINIT_CMD55) | (sdinit_cstate = SDINIT_ACMD41)/(sdinit_cstate = SDINIT_CMD1)| (sdinit_cstate = SDINIT_CMD16);/命令发送使能标志位，高有效wire cmd_rdboot_en = (sdinit_cstate = SD_RD_BPB) |

5、(sdinit_cstate =SD_RD_PT);/读愈SD启动if血能信号，高"效wire cmd_rdy = (cmd_nstate = CMD_CLKE) & spi_tx_rdy & spi_tx_enr);/命令发送完成标志位，高有效reg3:0 cmd_cstate;/发送命令当前状态寄存器reg3:0 cmd_nstate;/发送命令下一状态寄存器parameterCMD_IDLE= 4'd0,/无命令发送，等待状态CMD_NCLK= 4'd1,/上电初始化时需要产生74+CLK犬态CMD_CLKS= 4'd2,/产生 8 个

6、CLK状态CMD_STAR= 4'd3,/发送起始字节状态CMD_ARG1= 4'd4,/发送 arg31:24状态CMD_ARG2= 4'd5,/发送 arg23:16状态CMD_ARG3= 4'd6,/发送 arg15:8状态CMD_ARG4= 4'd7,/发送 arg7:0状态CMD_END= 4'd8,/发送结束字节状态CMD_RES= 4'd9,/接收口向应字节CMD_CLKE= 4'd10,/产生 8 个 CLK状态CMD_RD= 4'd11,/读 512Byte 状态CMD_DELAY= 4'd12;

7、/读写操作完成延时等待状态/状态转移always (posedge clk or negedge rst_n) if(!rst_n) cmd_cstate <= CMD_IDLE; else cmd_cstate <= cmd_nstate;/状态控制always (cmd_cstate or wait_cnt8 or cmd_clk or cmd_en or spi_tx_rdy or spi_rx_rdy or nclk_cnt or retry_repor sdinit_cstate or spi_tx_enr or spi_rx_enr or cmd_rdboot_en o

8、r cnt512or spi_rx_dbr) begincase(cmd_cstate)CMD_IDLE: beginif(wait_cnt8 = 8'hff)if(cmd_clk) cmd_nstate <= CMD_NCLK;else if(cmd_en | cmd_rdboot_en) cmd_nstate <= CMD_STAR;else cmd_nstate <= CMD_IDLE;else cmd_nstate <= CMD_IDLE;endCMD_NCLK: beginif(spi_tx_rdy && (nclk_cnt = 4&#

9、39;d11) && (!spi_tx_enr & !spi_rx_enr) cmd_nstate <= CMD_CLKE;else cmd_nstate <= CMD_NCLK;endCMD_CLKS: beginif(spi_tx_rdy && (!spi_tx_enr & !spi_rx_enr) cmd_nstate <= CMD_STAR;else cmd_nstate <= CMD_CLKS;endCMD_STAR: begin if(spi_tx_rdy && (!spi_tx_enr &am

10、p; !spi_rx_enr) cmd_nstate <= CMD_ARG1;else cmd_nstate <= CMD_STAR;endCMD_ARG1: beginif(spi_tx_rdy && (!spi_tx_enr & !spi_rx_enr) cmd_nstate <= CMD_ARG2;else cmd_nstate <= CMD_ARG1;endCMD_ARG2: beginif(spi_tx_rdy && (!spi_tx_enr & !spi_rx_enr) cmd_nstate <= CMD

11、_ARG3;else cmd_nstate <= CMD_ARG2;endCMD_ARG3: beginif(spi_tx_rdy && (!spi_tx_enr & !spi_rx_enr) cmd_nstate <= CMD_ARG4;else cmd_nstate <= CMD_ARG3;endCMD_ARG4: beginif(spi_tx_rdy && (!spi_tx_enr & !spi_rx_enr) cmd_nstate <= CMD_END;else cmd_nstate <= CMD_ARG4;

12、endCMD_END: beginif(spi_tx_rdy && (!spi_tx_enr & !spi_rx_enr) cmd_nstate <= CMD_RES;else cmd_nstate <= CMD_END;endCMD_RES: beginif(retry_rep = 8'hff) cmd_nstate <= CMD_IDLE;/响应超时，返回 IDLE 重新发起命令if(spi_rx_rdy && (!spi_tx_enr & !spi_rx_enr) begincase(sdinit_cstate)S

13、D_RD_PT,SD_RD_BPB:if(spi_rx_dbr = 8'hfe) cmd_nstate <= CMD_RD;/ 接收到 RD命令的起始字节 8'hfe,立即读取后面的512Belse cmd_nstate <= CMD_RES;SDINIT_CMD0,SDINIT_CMD55,SDINIT_ACMD41,SDINIT_CMD16:if(spi_rx_dbr = 8'hff) cmd_nstate <= CMD_RES;else cmd_nstate <= CMD_CLKE;/产生正确响应，结束当前命令default: cmd_nstate <= CMD_CLKE;endcaseendelse cmd_nstate <= CMD_RES;endCMD_CLKE: beginif(spi_tx_rdy && (!spi_tx_enr & !spi_rx_enr) cmd_nstate <= CMD_IDLE;else