基于单片机外文翻译、中英文翻译、外文文献翻译

1、英文原文descriptionthe at89s52 is a low-power, high-performance cmos 8-bit microcomputer with 4k bytes of flash programmable and erasable read only memory perom and128 bytes ram. the device is manufactured using atmel s high density nonvolatilememory technology and is compatible with the industry standa

2、rd mcs5-1. instruction set and pinout. the chip combines a versatile 8-bit cpu with flash on a monolithic chip, the atmel at89s52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.features:. compatible with mcs-51. products

3、. 4k bytes of in-system reprogrammable flash memory. endurance: 1,000 write/erase cycles. fully static operation: 0 hz to 24 mhz. three-level program memory lock. 128 x 8-bit internal ram. 32 programmable i/o lines. two 16-bit timer/counters. six interrupt sources. programmable serial channel. low p

4、ower idle and power down modesthe at89s52 provides the following standard features: 4k bytes of flash, 128 bytes of ram, 32 i/o lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry.in addition, the at89s52

5、 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/counters, serial port and interrupt system to continue functioning. the power down mode saves the ram contents but fr

6、eezes the oscillator disabling all other chip functions until the next hardware reset.pin description:vccsupply voltage. gndground.port 0port 0 is an 8-bit open drain bidirectional i/o port. as an output port each pin can sink eight ttl inputs. when is are written to port 0 pins, the pins can be use

7、d as high impedance inputs.port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. in this mode p0 has internal pullups.port 0 also receives the code bytes during flash programming, and outputs thecode bytes during program ve

8、rification. external pullups are required during program verification.port 1port 1 is an 8-bit bidirectional i/o port with internal pullups. the port 1 output buffers can sink/source four ttl inputs. when 1s are written to port 1 pins they are pulled high by the internal pullups and can be used as i

9、nputs. as inputs, port 1 pins that are externally being pulled low will source current iil because of the internal pullups.port 1 also receives the low-order address bytes during flash programming and verification.port 2port 2 is an 8-bit bidirectional i/o port with internal pullups. the port 2 outp

10、ut buffers can sink/source four ttl inputs. when 1s are written to port 2 pins they are pulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current iil because of the internal pullups.port 2 emits the high-order addre

11、ss byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses movx dptr. in this application it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses movx ri, port 2 emits the conte

12、nts of the p2 special function register.port 2 also receives the high-order address bits and some control signals during flash programming and verification.port 3port 3 is an 8-bit bidirectional i/o port with internal pullups. the port 3 output buffers can sink/source four ttl inputs. when 1s are wr

13、itten to port 3 pins they are pulled high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current iil because of the pullups.port 3 also serves the functions of various special features of the at89s52 as listed below:port pin

14、alternate functionsp3.0rxd serial input portp3.1txd serial output portp3.2int0 external interrupt0p3.3int1 external interrupt1p3.4t0 timer0 external inputp3.5t1 timer1 external inputp3.6wr external data memory write strobep3.7rd external data memory read strobewhile the oscillator is running resets

15、the device.ale/progport 3 alsoreceives some control signals for flash programming and verification.rstreset input. a high on this pin for two machine cyclesaddress latch enable output pulse for latching the low byte of the addressduring accesses to external memory. this pin is also the program pulse

16、 input prog during flash programming.in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory.if desired, ale operation can

17、be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is weakly pulled high. setting the ale-disable bit has no effect if the microcontroller is in external execution mode.psenprogram store enable is the read stro

18、be to external program memory.when the at89s52 is executing code from external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory.ea/vppexternal access enable. ea must be strapped to gnd in order to enab

19、le the device to fetch code from external program memory locations starting at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, ea will be internally latched on reset.ea should be strapped to vcc for internal program executions.this pin also receives the 12-volt programming enable

20、 voltagevpp during flash programming, for parts that require 12-volt vpp.xtal1input to the inverting oscillator amplifier and input to the internal clock operating circuit.xtal2output from the inverting oscillator amplifier.oscillator characteristicsxtal1 and xtal2 are the input and output, respecti

21、vely, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure1. either a quartz crystal or ceramic resonator may be used. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 2. the

22、re are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through adivide-by-two flip-flop, but minimum and maximum voltage high and low timespecifications must be observed.idle modein idle mode, the cpu puts itself to sleep while al

23、l the onchip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset.it should be noted that when idle is term

24、inated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access tointernal ram in this event, but access to the port pins is not inhibited. to eliminate th

25、e possibility of an unexpected write to a port pin when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory.status of external pins during idle and power down modesmodeprogram memoryalepsenportportportport

26、0123idleinternal11datadatadatadataidleexternal11floatdatadatadatapower downinternal00datadatadatadatapower downexternal00floatdatadatadatapower down modein the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. the on-chip ram and

27、 special function registers retain their values until the power down mode is terminated. the only exit from power down is a hardware reset. reset redefines the sfrs but does not change the on-chip ram. the reset should not be activated before vcc is restored to its normal operating level and must be

28、 held active long enough to allow the oscillator to restart and stabilize.program memory lock bitson the chip are three lock bits which can be left unprogrammed u or can be programmed p to obtain the additional features listed in the table below:lock bit protection modeswhen lock bit 1 is programmed

29、, the logic level at the ea pin is sampled and latched during reset. if the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. it is necessary that the latched value of ea be in agreement with the current logic level at that

30、pin in orderfor the device to function properly. programming the flash ：the at89s52 is normally shipped with the on-chip flash memory array in theerased state that is, contents = ffh and ready to be programmetdh. e programming interface accepts either a high-voltage 12-volt or a low-voltage vcc prog

31、ram enable signal.the low voltage programming mode provides a convenient way to program the at89s52inside the user s system, while t-hveolhtaigghe programming mode is compatible with conventional third party flash or eprom programmers.the at89s52 is shipped with either the high-voltage or low-voltag

32、e programming mode enabled. the respective top-side marking and device signature codes are listed in the following table.top-side markvpp=12vat89s52xxxx yywwvpp=5vat89s52xxxx-5 yywwsignature030h=1eh030h=1eh031h=51h031h=51h032h=ffh032h=05hthe at89s52 code memory array is programmed byte-bybyte in eit

33、her programming mode. to program any nonblank byte in the on-chip flash programmable and erasable read only memory, the entire memory must be erased using the chip erase mode.programming algorithm:before programming the at89s52, the address, data and control signals should be set up according to the

34、 flash programming mode table and figures 3 and 4. to program the at89s52, take the following steps.1. input the desired memory location on the address lines.2. input the appropriate data byte on the data lines.3. activate the correct combination of control signals.4. raise ea/vpp to 12v for the hig

35、h-voltage programming mode.5. pulse ale/prog once to program a byte in the flash array or the lock bits. the byte-write cycle is self-timed and typically takes no more than 1.5 ms. repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is rea

36、ched.data polling: the at89s52 features data polling to indicate the end of a write cycle. during a write cycle, an attempted read of the last byte written will result in the complement of the written datum on po.7. once the write cycle has been completed, true data are valid on all outputs, and the

37、 next cycle may begin. data polling may begin any time after a write cycle has been initiated.ready/busy: the progress of byte programming can also be monitored by therdy/bsy output signal. p3.4 is pulled low after ale goes high during programming to indicate busy. p3.4 is pulled high again when pro

38、gramming is done to indicate ready.program verify:if lock bits lb1 and lb2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. the lock bits cannot be verified directly. verification of the lock bits is achieved by observing that their

39、 features are enabled.chip erase : the entire flash programmable and erasable read only memoryarray is erased electrically by using the proper combination of control signals and byholding ale/prog low for 10 ms. the code array is written with all“ 1” s. the chi erase operation must be executed befor

40、e the code memory can be re-programmed.reading the signature bytes : the signature bytes are read by the same procedure as a normal verification of locations 030h, 031h, and 032h, except that p3.6 and p3.7 must be pulled to a logic low. the values returned are as follows.030h = 1eh indicates manufac

41、tured by atmel 031h = 51h indicates 89c51032h = ffh indicates 12v programming 032h = 05h indicates 5v programming programming interfaceevery code byte in the flash array can be written and the entire array can be erased by using the appropriate combination of control signals. the write operation cyc

42、le is selftimed and once initiated, will automatically time itself to completion.中文翻译描述at89s52 是美国 atmel公司生产的低电压，高性能 cmos位8单片机，片内含4kbytes 的快速可擦写的只读程序储备器（ pero）m和 128 bytes的随机存取数据储备器（ ram），器件采纳 atmel公司的高密度、非易失性储备技术生产，兼容 标准 mcs-51产品指令系统， 片内置通用 8 位中心处理器 （cpu）和 flish储备单元，功能强大 at89s52 单片机可为您供应很多高性价比的应用场合

43、， 可敏捷应用于各种掌握领域；主要性能参数：与 mcs-51产品指令系统完全兼容4k 字节可重复写 flash闪速储备器1000 次擦写周期全静态操作： 0hz24mhz 三级加密程序储备器 128*8 字节内部 ram32 个可编程 i/o 口2 个 16 位定时计数器6 个中断源可编程串行 uart通道低功耗闲暇和掉电模式功能特性概述at89s52供应以下标准功能： 4k 字节 flish 闪速储备器， 128 字节内部 ram， 32 个 i/o 口线，两个 16 位定时计数器，一个5 向量两级中断结构，一个全双工串行通信口，片内振荡器准时钟电路；同时，at89s52 可降至 0hz的静

44、态规律操作，并支持两种软件可选的节电工作模式； 闲暇方式停止 cpu的工作， 但答应ram，定时计数器，串行通信口及中断系统连续工作；掉电方式储存ram中的内容，但振荡器停止工作并禁止其它全部部件工作直到下一个硬件复位；方框图引脚功能说明vcc：电源电压gnd：地p0 口：p0口是一组 8 位漏极开路型双向 i/o 口，也即地址 / 数据总线复位口；作为输出口用时，每位能吸取电流的方式驱动8 个规律门电路，对端口写“ 1” 可 作为高阻抗输入端用；在拜访外部数据储备器或程序储备器时，这组口线分时转换地址（低8位）和数据总线复用，在拜访期间激活内部上拉电阻；p1 口：p1 是一个带内部上拉电阻的

45、 8 位双向 i/o 口， p1 的输出缓冲级可驱动（吸取或输出电流） 4 个 ttl规律门电路；对端口写“ 1”，通过内部的上拉电阻把端口拉到高电平， 此时可做熟出口； 做输出口使用时， 由于内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（ iil ）.flash 编程和程序校验期间， p1 接受低 8 位地址；p2 口：p2 是一个带有内部上拉电阻的 8 位双向 i/o 口， p2 的输出缓冲级可驱动（吸取或输出电流） 4 个 ttl 规律门电路；对端口写“ 1”，通过内部地山拉电阻把端口拉到高电平， 此时可作为输出口， 作输出口使用时， 由于内部存在上拉电阻，某个引脚被外部信号

46、拉低时会输出一个电流（ iil ）；在拜访外部程序储备器获 16 位地址的外部数据储备器（例如执行 movx dpt指r 令） 时，p2 口送出高 8 位地址数据； 在拜访 8 位地址的外部数据储备器（如执行 movx r指i 令）时， p2 口线上的内容（也即特别功能寄存器（ sfr）区中 r2 寄存器的内容），在整个拜访期间不转变；flash 编程或校验时， p2 亦接受高地址和其它掌握信号；p3 口：p3 口是一组带有内部上拉电阻的 8 位双向 i/o 口；p3 口输出缓冲级可驱动（吸取或输出电流） 4 个 ttl规律门电路；对 p3 口写入“ 1”时，他们被内部上拉电阻拉高并可作为输出

47、口；做输出端时，被外部拉低的p3 口将用上拉电阻输出电流（ iil）；p3 口除了作为一般的i/o口线外，更重要的用途是它的其次功能，如下表所示：端口引脚其次功能p3.0rxd 串行输入口 p3.2int0 外中断 0p3.3int1 外中断 1p3.4t0 定时/ 计数器 0p3.5p3.6t1 定时/ 计数器 1wr 外部数据储备器写选通p3.7rd 外部数据储备器读选通p3.1txd 串行输出口 p3 口仍接收一些用于 flash闪速储备器编程和程序校验的掌握信号；rst： 复 位 输入；当振荡器工作时，rst引脚显现两个机器周期以上高电平将使单片机复位；ale/pro：g 当拜访外部程

48、序储备器或数据储备器时，ale（地址所存答应）输出脉冲用于所存地址的低 8 位字节；即使不拜访外部储备器， ale仍以时钟振荡频率的 1/6 输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的；要留意的是：每当拜访外部数据储备器时将跳过一个ale脉冲；对 flash储备器编程期间，该引脚仍用于输入编程脉冲（prog）；如有不要，可通过对特别功能寄存器（ sfr）区中的 8eh单元的 d0 位置位， 可禁止 ale操作；该外置位后， 只要一条 movx和 movc指令 ale才会被激活； 此外，该引脚会被柔弱拉高，单片机执行外部程序时，应设置 ale无效；psen：程序储备答应（ psen

49、）输出是外部程序储备器的读选通信号，当 at89s52 由外部程序储备器取指令 （或数据） 时，每个机器周期两个 psen有效， 即输出两个脉冲；在此期间，当拜访外部数据储备器，这两次有效的psen信号不显现；ea/vpp:外部 拜访 答应； 欲 使 cpu 仅访 问外 部程序存 储器（ 地 址为0000h-ffffh），ea端必需保持低电平（接地） ；需留意的是 ; 假如加密位 lb1被编程，复位时内部会锁存 ea端状态；如 ea 端为高电平（接 vcc端）， cpu就执行内部程序储备器中的指令；flash 储备器编程时，该引脚加上 +12v的编程答应电源 vpp，当然这必需是该器件是使用

50、12v 编程电压 vpp.xtal1: 振荡器反相放大器的及内部时钟发生器的输出端；xtal2: 振荡器反相放大器的输出端；时钟振荡器 ：at89s52 中有一个用于构成内部振荡器的高增益反相放大器，引脚xtal1和xtal2分别是该放大器的输入端和输出端； 这个放大器与作为反馈的片外石英晶体或陶瓷谐振器一起构成自激振荡器，振荡电路参见图5；外接石英晶体（或陶瓷谐振器）及电容c1、c2 接在放大器的反馈回路中构成并联振荡电路；对外接电容c1、c2 虽然没有非常严格的要求，但电容容量的大小会稍微影响振荡频率的高低、 振荡器的稳固性、 起振的难易程度及温度稳固性，假如使用石英晶体，我们举荐电容使用

51、30pf+10pf，而如使用陶瓷谐振器建议挑选 40pf+10pf；用户也可以采纳外部时钟； 采纳外部时钟的电路如图 5 右所示；这种情形下， 外部时钟脉冲接到 xtal1端，即内部时钟发生器的输入端， xtal2就悬空由于外部时钟信号是通过一个 2 分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特别要求， 但最小高电平连续时间和最大的低电平连续时间应符合产品技术要求；闲暇模式 :在闲暇工作模式状态， cpu 保持睡眠状态而全部片内的外设仍保持激活状态，这种方式由软件产生； 此时，片内 ram和全部特别功能寄存器的内容保持不变；闲暇模式可由任何答应的中断恳求或硬件复位终止；终止

52、闲暇工作模式的方法有两种，其一是任何一条被答应中断的大事被激 活，即可终止闲暇工作模式；程序会第一响应中断，进入中断服务程序，执行完中断服务程序并仅随终端返回指令， 下一条要执行的指令就是使单片机进入闲暇模式那条指令后面的一条指令；其二是通过硬件复位也可将闲暇工作模式终止，需要留意的是，当由硬件复位来终止闲暇模式时，cpu通常是从激活闲暇模式那条指令的下一条指令开头连续执行程序的， 要完成内部复位操作， 硬件复位脉冲要保持两个机器周期（ 24 个时钟周期）有效，在这种情形下，内部禁止cpu拜访片内 ram，而答应拜访其它端口；为了防止可能对端口产生以外写入，激活空 闲模式的那条指令后一条指令不

53、应当是一条对端口或外部储备器的写入指令；闲暇和掉电模式外部引脚状态模式程序储备器alepsen port0 port1port2 port3闲暇模式内部11数据数据数据数据闲暇模式外部11浮空数据数据数据掉电模式内部00数据数据数据数据掉电模式外部00浮空数据数据数据掉电模式 :在掉电模式下， 震荡器停止工作， 进入掉电模式的指令是最终一条被执行的指令，片内 ram和特别功能寄存器的内容在终止掉电模式前被冻结；退出掉电模 式的唯独方法是硬件复位， 复位后将重新定义全部特别功能寄存器但不转变ram中的内容， 在 vcc复原到正常工作电平前， 复位应无效， 且必需保持肯定时间以使振荡重视启动并稳固工作；程序储备器的加密 ：at89s52可使用对芯片上的 3 个