着名半导体公司DFTATPG课件

1、ATPG Introduction for IP Team AgendaAgendaDFT RulesCombinational LoopAsynchronous ResetTri-state Bus ContentionClock DividersClock GatingDFT signalsFor ScanFor debugSoft IP tasks and deliverablesScripts and DemosQ&AWhats it?DFTStructured DFTATPGTerminology in ScanScan cell Scan chainScan procedu

2、reScan waveformScan typeScan fault modelScan CoverageAgendaAgendaDFT RulesCombinational LoopAsynchronous ResetTri-state Bus ContentionClock DividersClock GatingDFT signalsFor ScanFor debugSoft IP tasks and deliverablesScripts and DemosQ&AWhats it?DFTStructured DFTATPGTerminology in ScanScan cell

3、 Scan chainScan procedureScan waveformScan typeScan fault modelScan CoverageDesign Verification, Testing and DiagnosisDesign Verification, Testing and DiagnosisDesign Verification: Be sure the design perform its specified behavior.Before silicon.Testing: Exercise the system and analyze the response

4、to ascertain whether it behaves correctly.After silicon.Diagnosis: To locate the cause of misbehavior after the incorrect behavior is detected.After silicon. before siliconafter siliconproductionengineeringWhats DFTWhats DFTDFT (Design For Test)Testability is a design attribute that measures how eas

5、y it is to create a program to comprehensively test a manufactured designs quality. Traditionally, design and test processes were kept separate, with test considered only at the end of the design cycle. But in contemporary design flows, test merges with design much earlier in the process, creating w

6、hat is called a design-for-test (DFT) process flow. Testable circuitry is both controllable and observable. In a testable design; setting specific values on the primary inputs results in values on the primary outputs which indicate whether or not the internal circuitry works properly. To ensure maxi

7、mum design testability, designers must employ special DFT techniques at specific stages in the development process.Whats Structured DFT?Whats Structured DFT?Structured DFT Provides systematic and automatic approach to enhancing design testability. Goal is to increase the controllability and observab

8、ility of a circuit.Methods: scan design technique, which modifies the internal sequential circuitry of the design. Built-in Self-Test (BIST) method, which inserts a devices testing function within the device itself.boundary scan, which increases board testability by adding circuitry to a chip. Whats

9、 ATPGWhats ATPGATPG (Automatic Test Pattern Generation) Test patterns (test vectors), are sets of 1s and 0s placed on primary input pins during the manufacturing test process to determine if the chip is functioning properly. ATE (Automatic Test Equipment) determines if the circuit is free from manuf

10、acturing defects by comparing the fault-free outputwhich is also contained in the test patternwith the actual output measured by the ATE.Goal : create a set of patterns that achieves a given test coverage. Then run it on Tester. Pass indicated no related defects exist in this chip.AgendaAgendaDFT Ru

11、lesCombinational LoopAsynchronous ResetTri-state Bus ContentionClock DividersClock GatingDFT signalsFor ScanFor debugSoft IP tasks and deliverablesScripts and DemosQ&AWhats it?DFTStructured DFTATPGTerminology in ScanScan cell Scan chainScan procedureScan waveformScan typeScan fault modelScan Cov

12、erageSCAN Cell / SCAN ChainSCAN Cell / SCAN ChainScan Cell In normal operation (sc_en = 0), system data passes through the multiplexer to the D input of the flip-flop, and then to the output Q. In scan mode (sc_en = 1), scan input data (sc_in) passes to the flip-flop, and then to the scan output (sc

13、_out).Scan ChainA set of serially linked scan cells. Each scan chain contains an external input pin and an external output pin that provide access to the scan cells.The scan chain length (N) is the number of scan cells within the scan chain.SCAN ProcedureSCAN ProcedureThe operating procedure of the

14、scan circuitry is as follows:1. Enable the scan operation to allow shifting (to initialize scan cells).2. After loading the scan cells, hold the scan clocks off and then apply stimulus to the primary inputs.3. Measure the outputs.4. Pulse the clock to capture new values into scan cells.5. Enable the

15、 scan operation to unload and measure the captured values while simultaneously loading in new values via the shifting procedure (as in step 1).Before ScanAfter ScanSCAN WaveformSCAN Waveformscan_clkscan_seLoadshift shift shiftLoad /Unloadshift shift shiftcapturecaptureLoad /UnloadcaptureLoad /Unload

16、captureUnloadSCAN TypesSCAN TypesFull ScanHighly automated process.Highly-effective, predictable method.Ease of use.Assured quality.Partial ScanReduced impact on area.Reduced impact on timing.More flexibility between overhead and fault coverage.Re-use of non-scan macros.Stuck-At Fault ModelStuck-At

17、Fault ModelExample: Single Stuck-At Faults for AND GateThe single stuck-at model is the most common fault model used in fault simulation, because of its effectiveness in finding many common defect types. The stuck-at fault models the behavior that occurs if the terminals of a gate are stuck at eithe

18、r a high (stuckat-1) or low (stuck-at-0) voltage. The fault sites for this fault model include the pins of primitive instances.All s-a-0 faults in the AND gate are equivalents-a-1 s-a-0s-a-1s-a-0s-a-1 s-a-0s-a-0s-a-0s-a-1s-a-1s-a-0s-a-1Possible Errors: 6Possible Errors: 4Stuck-At Coverage ReportStuc

19、k-At Coverage Report # DT -Test Coverage = #FU - #UU - #TI - #BL - #RE # DT -Fault Coverage = #FU Statistics report- #faults #faultsfault class (coll.) (total)- - -FU (full) 1171003 1824936- - -UC (uncontrolled) 32 84UO (unobserved) 946 1286DS (det_simulation) 3580 8011DI (det_implication) 4 10 (pro

20、tected) 1138170 1767804PU (posdet_untestable) 784 1806PT (posdet_testable) 34 42UU (unused) 3035 5344TI (tied) 2093 2201BL (blocked) 331 333RE (redundant) 8272 10462AU (atpg_untestable) 13722 27553- - -test_coverage 98.66% 98.30%fault_coverage 97.50% 97.31%atpg_effectiveness 99.91% 99.92%- - -Protec

21、ted Faults alone: test_coverage 98.35% 97.85%fault_coverage 97.20% 96.87%-#test_patterns 271#simulated_patterns 271CPU_time (secs) 18364.6- AgendaAgendaDFT RulesCombinational LoopAsynchronous ResetTri-state Bus ContentionClock DividersClock GatingDFT signalsFor ScanFor debugSoft IP tasks and deliver

22、ablesScripts and DemosQ&AWhats it?DFTStructured DFTATPGTerminology in ScanScan cell Scan chainScan procedureScan waveformScan typeScan fault modelScan CoverageCombinational Loop & Tri-state ButCombinational Loop & Tri-state ButCombinational LoopNotice that the A=1, B=0, C=1 state causes

23、unknown (oscillatory) behavior, which poses a testability problem.It should be avoid if possible.Tri-state Bus ContentionTri-state Bus is not permitted inside chip.Divided ClockDivided ClockSome designs contain uncontrollable clock circuitry; that is, internally-generated signals that can clock, set

24、, or reset flip-flops. If these signals remain uncontrollable, they could disturb sequential elements during scan shifting. Thus, the system cannot convert these elements to scan.new_clk = scan_mode? tst_clk : gen_clkAsync ResetAsync ResetTest Logic Added to Control Asynchronous Resetuse ipt_async_s

25、e to control the mux.new_rst = ipt_se_async_xxx? ext_rst : int_rstAsync Reset (2)Async Reset (2)For the case where both set and reset of a flop are internally generated, either set or reset shall be disabled during scan mode using ipt_mode_scan signal, while other can be muxed with hardreset using i

26、pt_se_async signal. Selection of disabling set/reset signal shall be decided having less combinational logic for getting better test coverage.Clock GatingClock GatingClock GatingWhen clk is pulsed from low to high, the latch is disabled and remains so as long as the clk signal stays high. Therefore,

27、 even if the output of dff1 changes from high to low as a result of the leading edge of the pulse, that value change cannot propagate through the latch and effect clk_en until clk goes low again, enabling the latch.Equally important, scan chains must operate correctly. You can force se to 1 in the l

28、oad_unload procedure; however, it must be done before any “apply shift” statement. The se signal must be controllable to 1 from the chips primary inputs (IC pins).In IP DFT guide this se signal is connected to ipt_se_gatedclkp.Clock Gating (2)Clock Gating (2)Clock Gating CellCPE+TEQDQAgendaAgendaDFT

29、 RulesCombinational LoopAsynchronous ResetTri-state Bus ContentionClock DividersClock GatingDFT signalsFor ScanFor debugSoft IP tasks and deliverablesScripts and DemosQ&AWhats it?DFTStructured DFTATPGTerminology in ScanScan cell Scan chainScan procedureScan waveformScan typeScan fault modelScan

30、CoverageDFT SignalsDFT SignalsDFT signalsIpt_mode_scan_xxxIpt_se_xxxIpt_se_async_xxxIpt_se_gatedclkn/p_xxxIpt_si/so_xxxIpt_dbg_tck_xxxIpt_dbg_trst_xxxIpt_dbg_tms_xxxIpt_dbf_tdi_xxxIpt_dbg_tdo_xxxPlease refer to Section 2.3 of AgendaAgendaDFT RulesCombinational LoopAsynchronous ResetTri-state Bus ContentionClock DividersClock GatingDFT signalsFor ScanFor debugSoft IP tasks and deliverablesScripts and DemosQ&AWhats it?DFTStructured DFTATPGTerminology in ScanScan ce