HDL语言的循环整数除法器

1、循环整数除法器*学院*级*系姓名：*学号：*指导老师：*目录一、除法器的基本原理与改进 第1页二，程序源代码及QuartusII仿真 第4页三，测试代码及Modelsim仿真 第8页四，DC综合部分 第11页五Astro版图及解释 第14页一，除法器的基本原理与改进本设计是基于传统的除法器的基础上改进而来的。传统除法器的设计：一、先取除数和被除数的正负关系，然后正值化被除数。传统除法器因为需要递减的关系，所以除数就取负值的补码，方便操作。二、被除数递减除数，每一次的递减，商数递增。三、直到被除数小于除数，递减过程剩下的是余数。四、输出的结果根据除数和被除数的正负关系。例如：10除以3其操作流程

2、就是：1,10-3 余7>3；2,7-3 余4>3；3,4-3 余1<3。即经过三次的运算比较，得出10÷3=3并且余1。此次运算需要三个时钟周期来进行比较运算，显然，随着被除数的增大，其所需的时钟周期会呈递增趋势，加入，被除数过大的话，其过多的时钟消耗将会减慢运算速度。改进的循环型除法器循环型的除法器，就是位操作的除法器。循环型的除法器是典型的除法器，假设除数和被除数的位宽为N位，那么除法器就会循环N次的除法操作。这样时钟消耗就不会随着被除数的增加而增加了，提高了计算的速度。假设被除数A = 7（0111），除数B = 2 ( 0010 )，它们均为4位位宽。那么

3、操作空间就是 temp 就是 2 * Width。temp Width - 1 : 0 是用来填充被除数，temp Width * 2 - 1：Width -1  是用与除数递减操作。为了方便操作，我们建立 5位位宽的s空间用来寄存除数B的负值补码形式。此外还要考虑同步操作，temp Width * 2 - 1：Width -1  和 除数B的递减操作应该发生别的空间，亦即diff空间。diff空间和temp操作空间拥有同样的位宽。 reg 7:0temp;reg 7:0diff;reg 4:0s; 首先

4、初始化 temp空间和s空间。temp空间的 Width - 1 : 0  填入 被除数A，然而s空间用于寄存 除数B负值的补码形式。最后顺便清理diff空间。 temp <= 4'd0 , A ;s <= B3 ? B3 , B ? B3 , B + 1'b ;  /如果除数B为负值，就直接填入，                 

5、;                       /否则转换为负值后填入。diff <= 8'd0; s空间寄存B的负值的动作，其实是“小空间向大空间转换 + B绝对负值化”。  接下来的动作，是核心的部分。每一次的操作： 一、在diff空间先取 temp Width * 2 - 1 : Widt

6、h - 1 - B 或者 temp 7:3 + s二、然后判断diff空间的“最高位”, 亦即符号位，是逻辑1还是逻辑0。三、如果是逻辑1表示temp7:3 的值小于除数B，temp空间左移一位补0。反之如果是逻辑0，表示 temp7:3 的值大于除数B，temp空间被赋予diff空间的值，并且左移一位补1。 case( i ).1,2,3,4:  / 因为除数B和被除数A的位宽均为4位，所以循环4次。begin    diff = temp + s ,

7、3'b0 ;  / “=”表示当前步骤取得结果    if( diff7 ) temp <= temp 6:0, 1'b0;    else temp <= diff6:0 , 1'b1 ;    i <= i + 1'b1;end 当经过 4 次的循环操作后。temp空间的  Width - 1 : 0  是商数， Width * 2 -1: W

8、idth  是余数。在这里，重点是“=”这一段代码，diff取得的即时结果是在当前步骤，而不是在该步骤的未来。assign Quotient = temp3:0;assign Reminder = temp7:4;如下表所示：即得：7÷2=3余1。第25页二，程序源代码QuartusII仿真module luckyguy_divider (input clk, input rst, input start, input 7:0 dividend, input 7:0 divisor, output done, output 7:0 quotient, output 7:0

9、reminder, output 15:0 sq_diff, output 15:0 sq_temp ); reg 3:0 i; reg 8:0 s; reg 15:0 temp; reg 15:0 diff; reg isneg; reg isdone;always (posedge clk or negedge rst) if (!rst) begin i <= 4'd0; s <= 9'd0; temp <= 16'd0; diff <= 16'd0; isneg <= 1'b0; isdone <= 1'

10、;b0; end else if(start) case(i) 0: begin isneg <= dividend7divisor7; s <= divisor7 ? 1'b1, divisor:1'b1,divisor +1'b1; temp <= dividend7 ? 8'd0, dividend+1'b1:8'd0,dividend; diff <= 16'd0; i <= i + 1'b1; end 1,2,3,4,5,6,7,8: begin diff = temp + s,7'

11、d0; if(diff15) temp <= temp14:0,1'b0; else temp <=diff14:0,1'b1; i <= i +1'b1; end 9: begin isdone <= 1'b1; i <= i +1'b1; end 10: begin isdone <=1'b0; i <= 2'd0; end endcase assign done = isdone; assign quotient = isneg ? (temp7:0+1'b1):temp7:0; a

12、ssign reminder = temp15:8; assign sq_diff = diff; assign sq_temp = temp; endmodule例化模块：仿真波形：输入被除数和除数分别是25和4，得到的结果是商为6，余数为1，符合正确运算。其RTL电路：三，测试代码及Modelsim仿真timescale 1ps/1psmodule test_luckyguy_divider(); reg clk; reg rst; reg start; reg 7:0dividend; reg 7:0divisor; wire done; wire 7:0quotient; wire 7

13、:0reminder; wire 15:0sq_diff; wire 15:0sq_temp; initial begin rst=0;#0;rst=1; clk=0; forever #10 clk=clk; end reg 1:0i; always (posedge clk or negedge rst) if(!rst) begin i<=2'b00; dividend<=8'd0; divisor<=8'd0; start<=1'b0; end else case (i) 2'b00: if(done) begin sta

14、rt<=1'b0; i<=i+1'b1; end else begin dividend<=8'd8; /被除数为8 divisor<=8'b11111101;/除数为-3 start<=1'b1; end 2'b01: if(done) begin start<=1'b0; i<=i+1'b1; end else begin dividend<=8'b10000010; /被除数为-126 divisor<=8'b11111100;/除数为-4 start&l

15、t;=1'b1; end 2'b10: if(done) begin start<=1'b0; i<=i+1'b1; end else begin dividend<=8'd100;/被除数为100 divisor<=8'd25;/除数为4 start<=1'b1; end 2'b11: i<=4'd3; endcase luckyguy_divider m(.clk(clk),.rst(rst),.start(start),.dividend(dividend),.divisor(di

16、visor),.done(done),.quotient(quotient),.reminder(reminder),.sq_diff(sq_diff),.sq_temp(sq_temp); endmodule该测试代码一共有三组测试数据分别是：8 -3、-126 -4 、100 25。其结果分别是：商-2余2、商31余2、商4余0.四，DC综合部分Table I. DC synthesis resultstarget_librarylist cb13fs120_tsmc_max.db cb13io320_tsmc_max.dblink_librarycb13_tsmc_memory_max.

17、db cb13io320_tsmc_max.db cb13special.db cb13fs120_tsmc_max.db cb13fs120_tsmc_min.db cb13fs120_tsmc_typ.dbsymbol_librarygeneric.sdbsearch_path/home/sevidchang/softwares/synopsys/libraries/syn/home/sevidchang/softwares/synopsys/dw/sim_ver ./scripts ./libraries ./sourcesarea or gate accountNumber of po

18、rts: 68Number of nets: 330Number of cells: 275Number of references: 25Combinational area: 233434.187500Noncombinational area: 392.750000Net Interconnect area: 279.845215 Total cell area: 233826.812500Total area: 234106.781250powerCell Internal Power = 51.0636 mW (60%) Net Switching Power = 33.5905 m

19、W (40%) -Total Dynamic Power = 84.6541 mW (100%)Cell Leakage Power = 8.6295 uWnumber and types of constraint violations0max delay (met/violated/slack) data required time 9.81 data arrival time -6.87 - slack (MET) 2.94 min delay (met/violated/slack) data required time -0.06 data arrival time -0.58 -

20、slack (MET) 0.64Table II. Synthesis script(s)脚本文件：luckyguy.tcl# IMPORTANT:WHEN YOU INSERT IO PADS AUTOMATICALLY,YOU SHOULD ADD IO LIBRARY # (E.G.,"cb13io320_tsmc_max.db") TO YOUR "target_library" OF YOUR ".synopsys_dc.setup". # BUT WHEN YOU INSERT YOUR IO PADS MANUALLY

21、IN A TOP MODULE,YOU # SHOULD NOT ADD IO LIBRARY TO YOUR "target_library". # variables declarationset TOP luckyguy_dividerset MAPPED mappedset REPORTS_DIR reports# setup max/min libraryset_min_library cb13fs120_tsmc_max.db -min_version cb13fs120_tsmc_min.db# read in designread_verilog sourc

22、es/luckyguy_divider.vcurrent_design luckyguy_divider# insert padsset_port_is_pad all_inputsset_port_is_pad all_outputsset_pad_type -exact pc3c01 get_ports clkset_pad_type -exact pc3d01 remove_from_collection all_inputs get_ports clkset_pad_type -exact pc3o01 all_outputs# uniquify (MYNOTE:SHOULD BE A

23、 "uniquify" HERE IF THERE ARE MULTI-REFERENCES.)insert_pads# set constraint on designset_max_area 0create_clock -p 10 -n my_clock get_ports clkset_dont_touch_network get_clocks my_clock set_input_delay 0.6 -max -clock my_clock remove_from_collection all_inputs get_ports clkset_input_delay

24、0.0 -min -clock my_clock remove_from_collection all_inputs get_ports clk# NOTE:"-max/min" specifies that delay_value refers to the longest/shortest pathset_output_delay 0.6 -max -clock my_clock all_outputsset_output_delay -0.1 -min -clock my_clock all_outputsset_drive 0 all_inputsset_load

25、load_of cb13fs120_tsmc_max/bufbd1/I all_outputsset_operating_conditions -max cb13fs120_tsmc_maxset_max_transition 0.5 remove_from_collection all_inputs get_ports clkset_max_transition 0.5 all_outputs# compile designcurrent_design luckyguy_dividercompile# write the resultcurrent_design luckyguy_divid

26、erwrite -f db -hierarchy -output $MAPPED/$TOP.dbwrite -f verilog -hierarchy -output $MAPPED/$TOP.vwrite_sdf $MAPPED/$TOP.sdfwrite_script -output $MAPPED/$TOP.tclreport_timing -delay max -max_paths 1 -path full -nworst 1 > $REPORTS_DIR/timing_$TOP.rptreport_timing -delay min -max_paths 1 -path ful

27、l -nworst 1 >> $REPORTS_DIR/timing_$TOP.rptreport_area > $REPORTS_DIR/area_$TOP.rpt五Astro版图及解释版图管脚分配：一共有84个管脚，每面21个管脚，其中程序的输入输出共68个管脚，每面还有VDD与VSS各两个。1、 DC综合出的文件：luckyguy_divider.v：module luckyguy_divider_DW01_inc_8_0 ( A, SUM ); input 7:0 A; output 7:0 SUM; wire carry7 , carry6 , carry5 , c

28、arry4 , carry3 , carry2 , n1; ah01d0 U1_1_3 ( .A(A3), .B(carry3 ), .S(SUM3), .CO(carry4 ) ); ah01d0 U1_1_5 ( .A(A5), .B(carry5 ), .S(SUM5), .CO(carry6 ) ); ah01d0 U1_1_2 ( .A(A2), .B(carry2 ), .S(SUM2), .CO(carry3 ) ); ah01d0 U1_1_6 ( .A(A6), .B(carry6 ), .S(SUM6), .CO(carry7 ) ); ah01d0 U1_1_1 ( .A

29、(A1), .B(A0), .S(SUM1), .CO(carry2 ) ); ah01d0 U1_1_4 ( .A(A4), .B(carry4 ), .S(SUM4), .CO(carry5 ) ); xn02d1 U5 ( .A1(n1), .A2(carry7 ), .ZN(SUM7) ); inv0d1 U6 ( .I(A7), .ZN(n1) ); inv0d1 U7 ( .I(A0), .ZN(SUM0) );endmodulemodule luckyguy_divider_DW01_addsub_8_0 ( A, B, CI, ADD_SUB, SUM, CO ); input

30、 7:0 A; input 7:0 B; output 7:0 SUM; input CI, ADD_SUB; output CO; wire carry6 , carry5 , carry4 , carry3 , carry2 , carry1 , carry0 , B_AS6 , B_AS5 , B_AS4 , B_AS3 , B_AS2 , B_AS1 , B_AS0 , n1, n2, n3, n4, n5, n6, n7; 。 。 。 。 。 assign carry0 = B7; inv0d1 U229 ( .I(i3), .ZN(n208) ); pc3d01 U230 ( .P

31、AD(rst), .CIN(n70) ); pc3d01 U231 ( .PAD(start), .CIN(n71) ); pc3d01 U232 ( .PAD(dividend7), .CIN(n72) ); pc3d01 U233 ( .PAD(dividend6), .CIN(n73) ); pc3d01 U234 ( .PAD(dividend5), .CIN(n74) ); pc3d01 U235 ( .PAD(dividend4), .CIN(n75) ); pc3d01 U236 ( .PAD(dividend3), .CIN(n76) ); pc3d01 U237 ( .PAD

32、(dividend2), .CIN(n77) ); pc3d01 U238 ( .PAD(dividend1), .CIN(n78) ); pc3d01 U239 ( .PAD(dividend0), .CIN(n79) ); pc3d01 U240 ( .PAD(divisor7), .CIN(n80) ); pc3d01 U241 ( .PAD(divisor6), .CIN(n81) ); pc3d01 U242 ( .PAD(divisor5), .CIN(n82) ); pc3d01 U243 ( .PAD(divisor4), .CIN(n83) ); pc3d01 U244 (

33、.PAD(divisor3), .CIN(n84) ); pc3d01 U245 ( .PAD(divisor2), .CIN(n85) ); pc3d01 U246 ( .PAD(divisor1), .CIN(n86) ); pc3d01 U247 ( .PAD(divisor0), .CIN(n87) ); pc3o01 U248 ( .I(n259), .PAD(done) ); pc3o01 U249 ( .I(n260), .PAD(quotient7) ); pc3o01 U250 ( .I(n261), .PAD(quotient6) ); pc3o01 U251 ( .I(n

34、262), .PAD(quotient5) ); pc3o01 U252 ( .I(n263), .PAD(quotient4) ); pc3o01 U253 ( .I(n264), .PAD(quotient3) ); pc3o01 U254 ( .I(n265), .PAD(quotient2) ); pc3o01 U255 ( .I(n266), .PAD(quotient1) ); pc3o01 U256 ( .I(n267), .PAD(quotient0) ); pc3o01 U257 ( .I(n268), .PAD(reminder7) ); pc3o01 U258 ( .I(

35、n269), .PAD(reminder6) ); pc3o01 U259 ( .I(n270), .PAD(reminder5) ); pc3o01 U260 ( .I(n271), .PAD(reminder4) ); pc3o01 U261 ( .I(n272), .PAD(reminder3) ); pc3o01 U262 ( .I(n273), .PAD(reminder2) ); pc3o01 U263 ( .I(n274), .PAD(reminder1) ); pc3o01 U264 ( .I(n275), .PAD(reminder0) ); pc3o01 U265 ( .I

36、(n276), .PAD(sq_diff15) ); pc3o01 U266 ( .I(n277), .PAD(sq_diff14) ); pc3o01 U267 ( .I(n278), .PAD(sq_diff13) ); pc3o01 U268 ( .I(n279), .PAD(sq_diff12) ); pc3o01 U269 ( .I(n280), .PAD(sq_diff11) ); pc3o01 U270 ( .I(n281), .PAD(sq_diff10) ); pc3o01 U271 ( .I(n282), .PAD(sq_diff9) ); pc3o01 U272 ( .I

37、(n283), .PAD(sq_diff8) ); pc3o01 U273 ( .I(n284), .PAD(sq_diff7) ); pc3o01 U274 ( .I(n285), .PAD(sq_diff6) ); pc3o01 U275 ( .I(n286), .PAD(sq_diff5) ); pc3o01 U276 ( .I(n287), .PAD(sq_diff4) ); pc3o01 U277 ( .I(n288), .PAD(sq_diff3) ); pc3o01 U278 ( .I(n289), .PAD(sq_diff2) ); pc3o01 U279 ( .I(n290)

38、, .PAD(sq_diff1) ); pc3o01 U280 ( .I(n291), .PAD(sq_diff0) ); pc3o01 U281 ( .I(n268), .PAD(sq_temp15) ); pc3o01 U282 ( .I(n269), .PAD(sq_temp14) ); pc3o01 U283 ( .I(n270), .PAD(sq_temp13) ); pc3o01 U284 ( .I(n271), .PAD(sq_temp12) ); pc3o01 U285 ( .I(n272), .PAD(sq_temp11) ); pc3o01 U286 ( .I(n273),

39、 .PAD(sq_temp10) ); pc3o01 U287 ( .I(n274), .PAD(sq_temp9) ); pc3o01 U288 ( .I(n275), .PAD(sq_temp8) ); pc3o01 U289 ( .I(n292), .PAD(sq_temp7) ); pc3o01 U290 ( .I(n293), .PAD(sq_temp6) ); pc3o01 U291 ( .I(n294), .PAD(sq_temp5) ); pc3o01 U292 ( .I(n295), .PAD(sq_temp4) ); pc3o01 U293 ( .I(n296), .PAD

40、(sq_temp3) ); pc3o01 U294 ( .I(n297), .PAD(sq_temp2) ); pc3o01 U295 ( .I(n298), .PAD(sq_temp1) ); pc3o01 U296 ( .I(n299), .PAD(sq_temp0) ); luckyguy_divider_DW01_inc_8_0 add_66 ( .A(N151, N152, N153, N154, N155, N156, N157, N158), .SUM(N166, N165, N164, N163, N162, N161, N160, N159) ); luckyguy_divi

41、der_DW01_addsub_8_0 r154 ( .A(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, n131), .B(U71/U7/Z_0 , U71/U6/Z_6 , U71/U6/Z_5 , U71/U6/Z_4 , U71/U6/Z_3 , U71/U6/Z_2 , U71/U6/Z_1 , U71/U6/Z_0 ), .CI(1'b0), .ADD_SUB(U71/U7/Z_0 ), .SUM(N210, N209, N208, N207, N206, N205, N204,

42、N203) ); luckyguy_divider_DW01_addsub_16_0 r153 ( .A(U71/U2/Z_15 , U71/U2/Z_14 , U71/U2/Z_13 , U71/U2/Z_12 , U71/U2/Z_11 , U71/U2/Z_10 , U71/U2/Z_9 , U71/U2/Z_8 , U71/U2/Z_7 , 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0), .B(U71/U3/Z_15 , U71/U3/Z_14 , U71/U3/Z_13 , U71/U3/Z

43、_12 , U71/U3/Z_11 , U71/U3/Z_10 , U71/U3/Z_9 , U71/U3/Z_8 , U71/U3/Z_7 , U71/U3/Z_6 , U71/U3/Z_5 , U71/U3/Z_4 , U71/U3/Z_3 , U71/U3/Z_2 , U71/U3/Z_1 , U71/U3/Z_0 ), .CI(1'b0), .ADD_SUB(U71/U4/Z_0 ), .SUM(N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N1

44、75) );endmodule2、 Asrto管脚分配：luckyguy_divider.tdfdefine _cell (geGetEditCell); create power pads; Core power supply 。 。 。 。 。; dbCreateCellInst : Creates a cell instance in a cell.; SYNTAX:; dbCreateCellInst cellId "childLibName" "childCellName" "ce; llInstName" "ro

45、tationStr" "mirrorStr" Points "topCellName" tdfPurgePadConstr: instructs the Synopsys tool to delete all pin or pad ; location constraints created previously by pin or pad; functions. ; pad : Creates a TDF pad constraint with the specified values. ; SYNTAX:; pad <string p

46、adName> <string padSide> <int order>float o; ffset ; place the corner cellspad "cornerll" "bottom"pad "cornerur" "top"pad "cornerlr" "right"pad "cornerul" "left" place io and power padspad "U70"

47、"left" 1pad "U230" "left" 2pad "U231" "left" 3pad "U232" "left" 4pad "U233" "left" 5pad "U234" "left" 6pad "U235" "left" 7pad "U236" "left" 8pad "

48、;vdd1left" "left" 9pad "vdd2left" "left" 10pad "vss1left" "left" 11pad "vss2left" "left" 12pad "U237" "left" 13pad "U238" "left" 14pad "U239" "left" 15pad "U240

49、" "left" 16pad "U241" "left" 17pad "U242" "left" 18pad "U243" "left" 19pad "U244" "left" 20pad "U245" "left" 21pad "U246" "top" 1pad "U247" "top"

50、 2pad "U248" "top" 3pad "U249" "top" 4pad "U250" "top" 5pad "U251" "top" 6pad "U252" "top" 7pad "U253" "top" 8pad "vdd1top" "top" 9pad "vdd2top" "

51、;top" 10pad "vss1top" "top" 11pad "vss2top" "top" 12pad "U254" "top" 13pad "U255" "top" 14pad "U256" "top" 15pad "U257" "top" 16pad "U258" "top" 17pad "U259" "top" 18pad "U260" "top" 19pad "U261" "top" 20pad "U262" "top" 21pad "U263" "right" 1pad &quo