FPGA交通灯仿真及代码

1、控制模块设计'timescale1ns/1nsmoduleM_control(clk,rst,Leds,S_M,G_M,S_B,G_B);inputrst,clk;/Timeclockandresetoutput7:0Leds;/mainroadlightsLRYG,BranchlightsLRYG.output3:0S_M,G_M,S_B,G_B;/S_MmainroadshiweiG_Mismainrodgewei/S_BmainroadshiweiG_Bismainrodgeweireg7:0Leds;reg3:0S_M,G_M,S_B,G_B;reg7:0state;/S1?S

2、2.S8reg6:0count1,count2;/count1main,roadcount2branchparameterS1=8'b0_0_0_0_0_0_0_1,S2=8'b0_0_0_0_0_0_1_0,S3=8'b0_0_0_0_0_1_0_0,S4=8'b0_0_0_0_1_0_0_0,S5=8'b0_0_0_1_0_0_0_0,S6=8'b0_0_1_0_0_0_0_0,S7=8'b0_1_0_0_0_0_0_0,S8=8'b1_0_0_0_0_0_0_1;/always(posedgeclkorposedgerst)

3、beginif(rst)beginS_M<=0;G_M<=0;S_B<=0;G_B<=0;state<=S1;Leds<=8'b00010100;count1<=44;count2<=64;endelsebegincase(state)S1:if(count1=0)beginstate<=S2;Leds<=8'b00100100;/mainroadyellowbranchredcount1<=4;count2<=count2-1;endelsebegincount1<=count1-1;count2&

4、lt;=count2-1;endS2:if(count1=0)beginstate<=S3;count1<=9;count2<=count2-1;endelsebegincount1<=count1-1;count2<=count2-1;endS3:if(count1=0)beginstate<=S4;Leds<=8'b00100100;/mainroadyellowbranchredcount1<=4;count2<=count2-1;endelsebegincount1<=count1-1;count2<=count

5、2-1;endS4:if(count1=0&&count2=0)beginstate<=S5;Leds<=8'b01000001;/mainroadredbranchgreencount1<=59;count2<=19;endelsebegincount1<=count1-1;count2<=count2-1;endS5:if(count2=0)beginstate<=S6;Leds<=8'b01000010;/mainroadredbranchyellowcount1<=count1-1;count2<

6、;=4;endelsebegincount1<=count1-1;count2<=count2-1;endS6:if(count2=0)beginstate<=S7;Leds<=8'b01001000;/mainroadredbranchturnleftcount1<=count1-1;count2<=9;endelsebegincount1<=count1-1;count2<=count2-1;endS7:if(count2=0)beginstate<=S8;Leds<=8'b01000010;/mainroadre

7、dbranchyellowcount1<=count1-1;count2<=4;endelsebegincount1<=count1-1;count2<=count2-1;endS8:if(count1=0&&count2=0)beginstate<=S1;Leds<=8'b00010100;/mainroadgreenbranchredcount1<=44;count2<=64;endelsebegincount1<=count1-1;count2<=count2-1;enddefault:beginstat

8、e<=S1;Leds<=8'b00010100;/mainroadgreenbranchredcount1<=44;count2<=64;endendcaseendendalways(posedgeclk)beginS_M<=count1/10;G_M<=count1%10;S_B<=count2/10;G_B<=count2%10;endendmodule显示模块源代码'timescale1ns/1nsmodulexianshi(clk,rst,S_M,G_M,S_B,G_B,sel1,sel2,sel3,sel4);input

9、clk,rst;input3:0S_M,G_M,S_B,G_B;output6:0sel1,sel2,sel3,sel4;reg6:0sel1,sel2,sel3,sel4;always(posedgerstorposedgeclk)beginif(rst)beginsel1=7'b0000000;sel2=7'b0000000;sel3=7'b0000000;sel4=7'b0000000;endelsebegincase(S_M)4'b0000:sel1=7'b1111110;4'b0001:sel1=7'b0110000;4

10、'b0010:sel1=7'b1101101;4'b0011:sel1=7'b1111001;4'b0100:sel1=7'b0110011;4'b0101:sel1=7'b1011011;4'b0110:sel1=7'b1011111;4'b0111:sel1=7'b1110000;4'b1000:sel1=7'b1111111;4'b1001:sel1=7'b1111011;default:sel1=7'b1111110;endcasecase(G_M)4

11、'b0000:sel2=7'b1111110;4'b0001:sel2=7'b0110000;4'b0010:sel2=7'b1101101;4'b0011:sel2=7'b1111001;4'b0100:sel2=7'b0110011;4'b0101:sel2=7'b1011011;4'b0110:sel2=7'b1011111;4'b0111:sel2=7'b1110000;4'b1000:sel2=7'b1111111;4'b1001:s

12、el2=7'b1111011;default:sel2=7'b1111110;endcasecase(S_B)4'b0000:sel3=7'b1111110;4'b0001:sel3=7'b0110000;4'b0010:sel3=7'b1101101;4'b0011:sel3=7'b1111001;4'b0100:sel3=7'b0110011;4'b0101:sel3=7'b1011011;4'b0110:sel3=7'b1011111;4'b0111:s

13、el3=7'b1110000;4'b1000:sel3=7'b1111111;4'b1001:sel3=7'b1111011;default:sel3=7'b1111110;endcasecase(G_B)4'b0000:sel4=7'b1111110;4'b0001:sel4=7'b0110000;4'b0010:sel4=7'b1101101;4'b0011:sel4=7'b1111001;4'b0100:sel4=7'b0110011;4'b0101:s

14、el4=7'b1011011;4'b0110:sel4=7'b1011111;4'b0111:sel4=7'b1110000;4'b1000:sel4=7'b1111111;4'b1001:sel4=7'b1111011;default:sel4=7'b1111110;endcaseendendendmodule顶层模块'timescale1ns/1nsmodulejiaotong(clk,rst,Leds,S_M,G_M,S_B,G_B,sel1,sel2,sel3,sel4,enable);inputc

15、lk,rst,enable;output7:0Leds;output3:0S_M,G_M,S_B,G_B;output6:0sel1,sel2,sel3,sel4;wire3:0S_M,G_M,S_B,G_B,M_B;M_controlcontrol1(.clk(clk),.rst(rst),.Leds(Leds),.S_M(S_M),.G_M(G_M),.S_B(S_B),.G_B(G_B);xianshixianshi1(.clk(clk),.rst(rst),.S_M(S_M),.G_M(G_M),.S_B(S_B),.G_B(G_B),.sel1(sel1),.sel2(sel2),.sel3(sel3),.sel4(sel4);Endmodule测试代码'timescale1ns/1nsmoduletestJT;regclk,rst;wire7:0Leds;wi