VHDL整理,华工VHDL,数字系统设计,习题答案参考,试卷资料,电信学院大三

1、VHDL重点CPLD :Complex programmable logic devices (based on 乘积项)FPGA：Field Programmable Gate Arraybased on LUTPROM:与阵列固定，或阵列可编程(巧记，有个O，联想到or,所以是或)PLA：与或阵列均可编程巧记，pla,两个音，所以与或都有PAL，GAL：与阵列可编程，或阵列不可编程巧记，一个音，是与6.Digital system design is based on programmable logic devices (PLD).It is top-down design,suing

2、EDA.Strong capability of system descriptionIndependence of device and hardware techniqueIEEE standardFlexible design method(behav,struc,dataflow)Readable programAs an HDL,executed concurrentlystructurc of VHDL:目测填空题LIBRARY, Package, Entity, Architecture, Configuration, Block, Sub-program, Default Li

3、brary默认库:STD,workMOD取模，REM取余，ABS取绝对值，SLA算数左移SRA算数右移，SRL逻辑右移，SLL逻辑左移，ROR，ROLDifferent package-different physic circuit;Entity-outward appearenceArchitecture-describe the function or structure of the circuitInput-can not be assign the valueOutput-can not be the source of assignmentInout-bi-directional

4、 portBuffer-serve as an output,its value can be reloadedArchitecture descriptionBehavior descriptionData flow descriptionStructure description ,字符串用 19.实体名不能用数字开头，实体名要与文件名一致VHDL data typeInteger, real, natural, bit, bit_vector, std_logic, std_logic_vector, character, string, boolean, time, severity

5、levelZ high impedanceX forcing unknown自定义数组TYPE word8 IS ARRY (1 TO 8) OF BIT;VHDL data object: constant, variable, signalsignal:1.has corresponding hardware,2.global,for multiple process3.assignment has delay,4.can carry history information26.variable:1.has no corresponding hardware2.local,valid in

6、 its process only3.assignment takes effect immediately4.has current value only27.sequential statements should be packaged in process28.重点when .else是并行语句，不用process包起来，但是它是具有顺序性的，考试时一般考它与if语句的改写，注意，if语句是顺序语句，得用process包起来29.重点with.select是并行语句，也不用process包起来，它没有顺序性，且条件必须涵盖完全，也就是说假设没有全例举出来最后要有.when others

7、，考试一般考改写case语句注意：if语句和case也可以相互改写，要根据题目改写，书写顺序要小心，特别是优先级编码器PROCESS，注意，它是，只是它里面是一般考改写wait语句,有wait on+信号表和wait until+条件两种，注意，PROCESS还是要写的，只是不用加而已，别以为有wait就不能有PROCESS31.process的特点一般是选择题sequential statement(顺序语句)有if statement,case statement,loop statement,next statement,exit statement,wait statement,ret

8、urn,null两种电路的区别选择题考encoder和decoder要看清楚inputs是的是decoderinputs是的是encoder计算机存储信息和传输信息都是binary codes，所以encoder是为了方便要会画decoder和encoder的 Half adder里面，Sum用or, carry用andFull adder有和两种要会画sequential logic circuits同步Moore型就是同步的,同步可以消除亚稳态简单可靠，但是耗能异步(Mealy型就是异步的，容易出现亚稳态)D锁存器重名词解释分别为：锁存器，触发器，存放器，计数器，乘法器触发器 注意clk只

9、能是std_logic,不能是bit45.带复位和Qbar的D触发器要小心(考改错题) 考点2：复位是不用考虑时钟沿的， 所以写在时钟沿检测之前 考点3：Q和Qbar赋值放到PROCESS外面 考点1：加一个信号作为中间值其实但凡带bar的都是这样设一个signal作为中间值的，如果不这样做，直接在PROCESS用D给Q和用not D给Qbar赋值，综合时会综合成两个触发器。注意用signal才能放到PROCESS外，用variable的话就要放PORCESS里面，建议用signalregister存放器，D_F.F其实就是一个one bit的register这句赋值的意思是Q赋全0移位存放器

10、分别为串进串出，串进并出，并进串出，S是串，P是并串进并出的例子 串进，第n-1位被踢掉，所以最高位变成n-2位 并出State machine状态机 finite number of states有限种状态FSM就是有限状态的状态机其实它是用来描述sequential logic的 Next state logic一般用ns Combinational logicsequential logic Output logic(一般用op) Memory units(一般用seq)分别对Next state logic，Output logic，Memory units写进程，这就是课本分三进程的

11、分法，其中Next state logic，Output logic可以放在一个进程里，这样就是双进程的状态机了考试要求掌握双进程状态机Race and Hazard竞争与冒险Signals through different paths arrive at the same node with time difference because of different propagation delays, which may causes transient error in output说白了，就是没有同步，超级赛亚人合体没同步就会变成“变体所以防止竞争冒险可以用同步时序逻辑电路Race

12、and Hazard can be avoided by synchronous同步 sequential logicASM图的特点1.used for synchronous sequential system用于同步时序逻辑电路2.ASM can represent the exact timing relations between state transitions可以表现不同状态之间的时序关系3.It resembles software flow chart, but it has corresponding hardware structure.它有对应的硬件52，图重点ondi

13、tional output box条件框Decision box判断框State box状态框 R-0注意 表示R在状态末赋0值,然后保持，直到下次赋值 =1 和 一样，都是表示在这个状态时Z赋值1，过了这个状态就变为053.要会根据ASM图画波形图注意条件框与它所属的状态框是同一个状态的，画波形图的时候要小心54.要会根据电路图画ASM图重重重重点，大题方法，先根据电路图写驱动方程和输出方程，然后根据方程画状态转换表，再根据状态转换表画ASM图 一定要 搞 懂55.Moore machineThe output depends on the present state only，the ou

14、tput is solely a function of the present state.The output of Moore machine is independent of current inputThe output part and input part are separatedMealy Machine比Moore结构复杂，complicatedThe output depends on both the present state and the input，the output is a function of the present state and of inp

15、utIf the input changes, the output can change during the current state.57.One-process state machine单进程状态机State transition, next state logic, and output logic are included in a single process.58.two-process state machine双进程状态机大题重点，不解释LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY traffic IS PORT(

16、clock , timed , car : IN std_logic ; start_timer, major_green, minor_green : OUT std_logic );END ENTITY traffic ;ARCHITECTURE asm2 OF traffic ISTYPE state_type IS (G, R); -利用枚举类型定义状态SIGNAL pr_state, nx_state : state_type; -将状态机的现态、次态定义为全局信号，便于在进程间传递信息BEGINseq: PROCESS (clock)BEGIN IF(rising_edge(clo

17、ck) THEN pr_state = nx_state;-次态是存放器的输入 END IF; -条件涵盖不完整的if语句产生状态存放器END PROCESS seq; -产生状态存放器的进程com: PROCESS (pr_state, car, timed) BEGIN start_timer major_green = 1;minor_green = 0; IF (car = 1) THEN start_timer = 1; nx_state = R; ELSE nx_state major_green = 0; minor_green = 1; IF (timed= 1) THEN n

18、x_state = G; ELSE nx_state = R; END IF; END CASE;END PROCESS com;-产生次态和输出逻辑的进程END asm2;59.three-process state machine三进程状态机LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY traffic IS PORT( clock , timed , car : IN std_ulogic ; start_timer, major_green, minor_green : OUT std_ulogic );END ENTITY traf

19、fic ;ARCHITECTURE asm2 OF traffic ISTYPE state_type IS (G, R); -利用枚举类型定义状态SIGNAL pr_state, nx_state : state_type; -将状态机的现态、次态定义为全局信号，便于在进程间传递信息BEGINseq: PROCESS (clock)BEGIN IF(rising_edge(clock) THEN pr_state IF (car = 1) THEN nx_state = R; ELSE nx_state IF (timed = 1) THEN nx_state = G; ELSE nx_st

20、ate = R; END IF;END CASE;END PROCESS ns;op: PROCESS (car, pr_state) Mealy or Moore? -process for output logicBEGINstart_timer = 0;IF (pr_state = G) THEN major_green = 1; minor_green = 0; IF (car = 1) THEN start_timer = 1; END IF;ELSE major_green = 0; minor_green clk_t,rst = rst_t,q = q_t);STIMULUS:

21、processbegin rst_t = 0; wait for 100 ns; -0 fs这局部按题目要求产生信号，产生的时钟周期为100ns；复位信号0电平有效，且起始时刻为0,100ns后变为1。rst_t = 1;wait for 1 us; wait;end process; CLOCK: processbeginclk_t = 0;wait for 50 ns; clk_t = 1;wait for 50 ns; end process;end TB;Design optimization优化涉及race and hazard的知识涉及flip-flop，latch等的引入问题看课

22、本第七章P103P117avoid unwanted registers的方法1.Combinational logic description has no edge-triggered states2.Complete IF statement 3.Complete signal assignment in CASE statement, if a signal or variable is assigned a value in one branch, it should be assigned values in every branch, otherwise, it should b

23、e given a initial value before the execution of case statement.65.Set up time:To ensure reliable operation, the input to a register must be stable for a minimum time before the clock edgeHold time:To ensure reliable operation, the input to a register must be stable for a minimum time after the clock

24、 edge66.If a signal transition violates a registers tSUset up time or tH (hold time)requirements, the output of the register may go into a metastable state亚稳态67.In synchronous systems, the input signals must always meet the register timing requirements, so metastability does not occur.在同步系统中。没有亚稳态Sy

25、nthesis综合Synthesis levels:目测填空选择题 high level synthesis, 2.RTL synthesis, 3.logic synthesis, 4.layout synthesis69.High level synthesis：目测选择题translation from algorithmic(算法) behavior description to RTL description从算法级的行为描述转换到存放器传输级描述的过程Normally, the physic hardware structure for a high level descripti

26、on is not unique, the main objective of high level synthesis is to find an optimal structure with respect to the cost and constraints约束.综合结果不唯一，这点喜欢考选择题，选择题喜欢说它是唯一的，喜欢考选错误的，选它For the same VHDL description, different synthesis results may obtained depends on different synthesis tools.70.logic synthes

27、is：translation from RTL description to logic gate netlist网表要到达higherspeedscovering smallersurface areas做到它们的balance71.Constraints约束for synthesis can be described by user-defined attributes,which will be omitted in simulation 就是说仿真的时候你的那些约束条件是被忽略的注：芯片的surface areas和系统的speeds是主要的两个约束a process includes

28、 at most one clock signal一个process里只能有一个时钟信号Delay is omitted by most of existing synthesizer延时会被综合器忽略Synchronous design are preferred同步设计比拟受欢送76 A).type Boolean is (FALSE , TRUE);B).type State_type is (HALT,READY,RUN,ERROR);C).type Std_logic is (U,X,0, 1, Z, -);D).type My_integer is Integer range 0

29、to 255;E).subtype Byte_int is Integer range -128 to 127;tF).ype Word is array 31 downto 0) of Bit;G).type My_RAM is array (1023 downto 0 ) of Word;H).typeRegNameis(AX, BX, CX, DX);typeOperationisrecordMnemonic : String (1to10);OpCode : Bit_Vector(3downto0);Op1, Op2, Res : RegName;endrecord;If statem

30、ent can be synthesized into Mux or basic logic gates.Case statement is synthesized into Mux.Case statement needs more logic resourcesThe synthesis of the loop statement is complicated in high-level synthesis信号综合结果(1) S = A; -the resultant circuit is hardwire(2) R= 1; -R is synthesized as a constant (3) T function simulation-synthesize-adaptation-timing simu