系统结构实验报告

1、北京工业大学计算机学院系统结构实验报告07044101王文通2010-12-1系统结构实验系统结构实验 目录TOC o 1-5 h z HYPERLINK l bookmark2 o Current Document 目录2 HYPERLINK l bookmark4 o Current Document 实验一流水线中的相关3 HYPERLINK l bookmark6 o Current Document 一、实验目的3 HYPERLINK l bookmark8 o Current Document 二、实验原理3三、实验步骤3 HYPERLINK l bookmark10 o Curr

2、ent Document 四、实验总结5 HYPERLINK l bookmark12 o Current Document 实验二循环展开及指令调度6 HYPERLINK l bookmark14 o Current Document 一、实验目的6 HYPERLINK l bookmark16 o Current Document 二、实验原理6三、实验步骤6 HYPERLINK l bookmark18 o Current Document 1指令调度技术6 HYPERLINK l bookmark20 o Current Document 循环展开以及指令调度提高性能8 HYPERLI

3、NK l bookmark22 o Current Document 四、实验总结10 HYPERLINK l bookmark24 o Current Document 五、代码10 HYPERLINK l bookmark26 o Current Document 实验三cache性能分析13 HYPERLINK l bookmark28 o Current Document 一、实验目的13 HYPERLINK l bookmark30 o Current Document 二、实验原理13 HYPERLINK l bookmark32 o Current Document 三、实验过程

4、13 HYPERLINK l bookmark34 o Current Document 1基本配置情况下运行程序13 HYPERLINK l bookmark36 o Current Document 2改变Cache容量对Cache性能的影响；14 HYPERLINK l bookmark38 o Current Document 3改变Cache的相联度对Cache性能的影响；16 HYPERLINK l bookmark40 o Current Document 4改变Cache块大小对Cache性能的影响；18 HYPERLINK l bookmark44 o Current Doc

5、ument 5.不同的替换算法对Cache性能的影响。205.1不同容量下，不同的替换算法对Cache性能的影响205.2不同相联度下，不同的替换算法对Cache性能的影响23实验一流水线中的相关一、实验目的熟练掌握WinDLX模拟器的操作和使用，熟悉DLX指令集结构及其特点；加深对计算机流水线基本概念的理解；进一步了解DLX基本流水线各段的功能以及基本操作；加深对数据相关、结构相关的理解，了解这两类相关对CPU性能的影响；了解解决数据相关的方法，掌握如何使用定向技术来减少数据相关带来的暂停二、实验原理用WinDLX模拟器模拟流水线。1用WinDLX模拟器执行下列三个程序：求阶乘程序fact.

6、s求最大公倍数程序gcm.s求素数程序prim.s分别以步进、连续、设置断点的方式运行程序，观察程序在流水线中的执行情况，观察CPU中寄存器和存储器的内容。熟练掌握WinDLX的操作和使用。2.用WinDLX运行程序structure_d.s，通过模拟找出存在资源相关的指令对以及导致资源相关的部件；记录由资源相关引起的暂停时钟周期数，计算暂停时钟周期数占总执行周期数的百分比；论述资源相关对CPU性能的影响，讨论解决资源相关的方法。资源相关：IFI|Stall|ID|R-Stall11IFI|Stalladdd晌4ADDDF0,F0,F4ADDDF2,F0,F2;加法器sdddf2J0J2;ad

7、diADDDF2,F0,F2IIFI|Stall|ID|Fl-5扫ll|faddEXfl|MEMadddf2J0J2addir2j2,0 x8addisubr5j4j2ADDIR2,R2,#8;加法器IF|Stall|ID|intEX|Stall丄1ID汕1|IF|StallADDDADDIADDISUBF2,F0,F2R2,R2,#8;MEMR3,R3,#8;MEMR5,R4,R2;MEM由资源相关引起的暂停时钟周期数是50个（每次循环5个，共10次循环），暂停时钟周期数占总执行周期数的百分比50/139=35.97%资源相关降低CPU的性能，效率下降。资源相关引起的暂停，可以采取指令调度的

8、方法进行改进。3.在不采用定向技术的情况下（去掉Configuration菜单中EnableForwarding选项前的勾选符），用WinDLX运行程序data_d.s。记录数据相关引起的暂停时钟周期数以及程序执行的总时钟周期数，计算暂停时钟周期数占总执行周期数的百分比。数据相关：Total:202Cyclefs)executed.IDewecutedby85Instructiori(s).2InstnjctionfsjcurrentlyinPipeline.Hardwareconfiguration:Memorysize:32768BtesfaddE-Stges;1,requiredCycl

9、es;2fmulEX-Stages:1,requiredCycles:5fdivEX-Stages:Lre口山詁口匚虽19Forwardingdisabled.GtsilLs:RAWstalls:104(51.48ol剖CyclesWWstalls;00.00ofallCycles)Structuralstalls:(0.Q0SofvllCyclesControlstalls:9(4.46ofallCyclesTrapstalls:31.48ofallCycles)Total:116Stall(s(57.42oFallCycles数据相关引起的时钟周期数是104个，执行程序总时钟周期数是202

10、个。暂停时钟周期数占总执行周期数的百分比54.18%在采用定向技术的情况下（勾选EnableForwarding，用WinDLX再次运行程序data_d.s。重复上述3中的工作，并计算采用定向技术后性能提高的倍数。数据相关引起的时钟周期数是30个，执行程序总时钟周期数是128个。暂停时钟周期数占总执行周期数的百分比23.44%采用定向技术后性能提高202/128=1.58倍Statistics-I凶Total;亠128Cycle(s)&Mecuteci.IDexecutedby85Instruct!ori(s).2InstructionfsjcurrentlyinPipeline.Hardwa

11、reconfiguration:Memorysize:32766BtesfdddE-Stages:1requiredCycles:2fmulEX-Stages:1”requiredCycles:5fdivEX-Stages:1,requiredCycles:19ForwardingenabledStalls:RAW曲llw;30(23.44of冃IICycle?),thereof;LDstalls:20(GG.G7ofRAWstallsBranch/Junpstalls:10(33.33ofRAWstallsFloatingpointstalls:Cl(0.00MRAWstalls)WAV/s

12、talls:0(0.00ofallCycles)Structuralstalls:0(0.00ofallCycles)Controlstalls:3(7.03XofallCyclesTrapstalls:32.34%ofallCyclesTotal:425t3ll(s)32.81ofallCycles)_四、实验总结采用流水线技术会遇到：数据相关、控制相关、资源相关等问题。为解决数据相关引起的暂停，可以采用指令调度和定向技术的方法来避免。通过指令调度，使相关的数据执行距离拉开，使得不会发生数据相关。通过定向技术，可以将相关数据结果直接传送到所有需要它的功能单元的输入端，避免数据相关引起的暂停。

13、为解决控制相关引起的暂停，可以使用循环展开的方法来减少控制相关的次数。为解决资源相关引起的暂停，可以采用指令调度的方法来避免。通过指令调度，使相关的资源使用的距离拉开，使得不会发生资源相关。实验二循环展开及指令调度一、实验目的加深对循环级并行性、指令调度技术、循环展开技术以及寄存器换名技术的理解熟悉用指令调度技术来解决流水线中的数据相关的方法；了解循环展开、指令调度等技术对CPU性能的改进。二、实验原理用WinDLX模拟器模拟流水线。1指令调度技术(1)用DLX汇编语言编写代码文件*.s，程序中应包括数据相关与结构相关(假设：加法、乘法、除法部件各有2个，延迟时间都是3个时钟周期)通过菜单中的

14、pointstages”选项，把加法、乘法、除法部件的个数设置为2个，把延迟都设置为3个时钟周期；用WinDLX运行程序。记录程序执行过程中各种相关发生的次数、发生相关的指令组合，以及程序执行的总时钟周期数；采用指令调度技术对程序进行指令调度，消除相关；用WinDLX运行调度后的程序，观察程序在流水线中的执行情况，记录程序执行的总时钟周期数；(6)根据记录结果，比较调度前和调度后的性能。论述指令调度对于提高CPU性能的意义。改进之前：共用了76个周期共发生36次相关资源相关:9次数据相关:17次控制相关:7次Trap暂停:3次IIStatistics-n76Cycle(s)executed.I

15、Dexecutedby40Instruction(s).2InstructionfscurrentlyinPipeline.Hardwareconfiguration:Memorvsize:32760BytesfaddEX-Stages:2,requiredCycles:3fmulEX-Stages:2,requiredCycles:3fdivEX-Stages:2,requiredCycles:3Forwardingenabled.Stalls:RAWstalls:17(22.37ofallCycles),thereof:LDstalls:9(52.94：ofRAWstalls)Branch

16、/Jumpstalls:8(47.06ofRAWstalls)Floatingpointstalls:0(0.00ofRAWstallsWAWstalls:0(0.00：ofallCycles)Structuralstalls:0(0.00ofallCycles)Controlstalls:7(9.21ofallCvclesTrapstalls:3(3.95ofallCycles)Total:27Stall(s(35.53ofallCycles)讪门wO(r2)addr1addir7jO,OwSIFIDintEX|MEM|IFID|R-5tall|IF|Stall|LWR1,0(R2)ADDR

17、1,R1,R3;数据相关，1次ADDIR7,R0,8;资源相关，1次LWR5,0(R1)ADDIR5,R5,#10;数据相关，共发生8次ADDIR2,R2,#4;资源相关，共发生8次subir7j7,0 x1:bnez7SUBR7,R7,1BNEZR7,LOOP;数据相关，共发生8次bnezr7Joop；trapOmO:BNEZR7,LOOPTRAP#0;控制相关，共发生7次traziCxO:TRAP#0;Trap暂停3个周期IF|LStall2Instruction(s)currentlyinPipeline.指令调度后:共用了59个周期共发生10次相关控制相关:7次Trap暂停:3次Har

18、dwareconfiguration:Memorysize:32760BytesfaddEX-Stages:1,requiredCycles:2fmulEX-Stages:LrequiredCycles:5fdivEX-Stages:1,requiredCycles:19Forwardingenabled.Stalls:RAWstalls:0(0.00ofallCycles,thereof:LDstalls:0(0.00：ofRAWstalls)Branch/Jumpstalls:0(0.00ofRAWstalls)Floatingpointstalls:0(0.00ofRAWstallsWA

19、V/stalls:0(0.00：ofallCyclesStructuralstalls:0(0.00ofallCyclesControlstalls:7(11.06ofallCycles)Trapstalls:3(5.00ofallCyclesTotal:10Stall(s)(16.95：ofallCycles)指令调度后的加速比是76/59=1.29,通过指令调度，可以充分利用cpu部件利用率，减少数据相关和资源相关引起的暂停。bnezr7L00Ptrap0 x0IFIDabortedBNEZR7,LOOPTRAP#0;控制相关，共发生7次traziCxO:TRAP#0;Trap暂停3个周期

20、IF1T-Stall2.循环展开以及指令调度提高性能用DLX汇编语言编写代码文件*.s，程序中包含一个循环次数为4的整数倍的简单循环；用WinDLX运行该程序。记录执行过程中各种相关发生的次数以及程序执行的总时钟周期数；将循环展开3次，将4个循环体组成的代码代替原来的循环体，并对程序做相应的修改。然后对新的循环体进行寄存器换名和指令调度；用WinDLX运行修改后的程序，记录执行过程中各种相关发生的次数以及程序执行的总时钟周期数；根据记录结果，比较循环展开、指令调度前后的性能。Statistics单纯循环展开共用了58个周期共发生24次相关Tcitad:50Cclefsexecuted.IDex

21、ecutedby42Instructionfs,2InstructionfscurrentlyinPipeline.资源相关:9次数据相关:11次控制相关:1次Trap暂停:3次Hardwareconfiguration:Memorysize:32768BytesfaddEX-Stages:1,requiredCycles:2fmulEX-Stages:1,required匚yules:5fdivEX-Stages:LrequiredCycles:19Forwardingenabled.Stalls:RAWstalls:11(10.96ofallCycles),thereof:LDstalls

22、:9(01.02ofRAWstalls)Branch/Jumpstalls:2(18.10ofRAWstalls)Floatingpointstalls:0(0.00ofRAWstalls)WAWstalls:0(0.00：ofallCyclesStructuralstalls:0(0.00ofallCycles)Controlstalls:1(1.72ofallCycles)Trapstalls:3(5.11%ofallCyclesTotal:15Stall(s(25.86ofallCvcles)指令调度后的加速比是76/58=1.31,通过循环展开，可以充分利用cpu部件利用率，减少控制相

23、关引起的冲刷和数据相关引起的暂停。讪门nO(i2)addr1addir7jO,OH8IFIDirtEX|MEM|IFID|Fl-浪ll|IFIStall|LWR1,0(R2)ADDR1,R1,R3;数据相关，1次ADDIR7,R0,8;资源相关，1次wr5.0w0(r1:addirSjS.CiKa!addir2j2,0w4:LWR5,0(R1)ADDIR5,R5,#10;数据相关，共发生8次ADDIR2,R2,#4;资源相关，共发生8次subir7j7r0 x1:匕门已己7匚心匚|SUBR7,R7,1BNEZR7,LOOP;数据相关，共发生2次bnezFJocip；trap0 x0:BNEZR

24、7,LOOPTRAP#0;控制相关，共发生1次traziCxO:TRAP#0;Trap暂停3个周期循环展开+指令调度共用了47个周期共发生4次相关IF|T-Stall47Cycle(s)executed.IDexecutedby42Instruction(s).2Instruction(s)currentlyinPipeline.IIStatistics-nJHardwareconfiguration:Memorysize:32768BytesfaddEX-Stages:1,requiredCycles:2fmulEX-Stages:LrequiredCycles:5fdivEX-Stages

25、:1,requiredCycles:19Forwardingenabled.控制相关:1次Trap暂停:3次Stalls:RAWstalls:0(0.00ofallCycles),thereof:LDstalls:0(0.00ofRAWstalls)Elranch/Jumpstalls:0(0.00ofRAWstalls)Floatingpointstalls:0(0.00ofRAWstallsWAWstalls:0(0.00：ofallCyclesStructuralstalls:0(0.00ofallCycles)Controlstalls:1(2.13ofallCycles)Trapst

26、alls:3(6.38ofallCyclesTotal:4Stall(s(8.51ofallCycles指令调度后的加速比是76/47=1.62。bn52r700PtrapOwOIF|ID|intEXIF|abortedBNEZR7,LOOPIF|LStallTRAP#0;控制相关，共发生1次traziCxO:TRAP#0;Trap暂停3个周期四、实验总结循环展开和指令调度都能提高cpu性能，减少暂停，但是两者同时进行改进时，优化性能并不是单纯的相加。因为循环展开的改进也会减少和循环判断有关的数据相关。同时，循环展开和指令调度对cpu性能提高的能力也因不同程序而异，若循环次数较多，则采取循环展

27、开获得的cpu性能提升较高，若数据相关、资源相关较多，则采取指令调度获得的cpu性能提升较高。五、代码改进前代码：LHIR2,(A16)&0XFFFFADDUIR2,R2,A+8LHIR3,(B16)&0XFFFFADDUIR3,R3,B&0XFFFFLWR1,0(R2)ADDR1,R1,R3ADDIR7,R0,8LOOP:LWR5,0(R1)ADDIR5,R5,#10ADDIR2,R2,#4SUBR7,R7,1BNEZR7,LOOPTRAP#0A:.WORD0,4,8,12,16,20,24,28,32,36B:.WORD9,8,7,6,5,4,3,2,1,0指令调度后代码:LHIR2,(A

28、16)&0XFFFFADDUIR2,R2,A+8LHIR3,(B16)&0XFFFFADDUIR3,R3,B&0XFFFFLWR1,0(R2)ADDIR7,R0,8ADDR1,R1,R3LOOP:LWR5,0(R1)ADDIR2,R2,#4SUBR7,R7,1ADDIR5,R5,#10BNEZR7,LOOPTRAP#0A:.WORD0,4,8,12,16,20,24,28,32,36B:.WORD9,8,7,6,5,4,3,2,1,0循环展开后代码:LHIR2,(A16)&0XFFFFADDUIR2,R2,A+8LHIR3,(B16)&0XFFFFADDUIR3,R3,B&0XFFFFLWAD

29、DADDILOOP:LWADDIADDISUBLWADDIADDISUBLWR1,0(R2)R1,R1,R3R7,R0,8R5,0(R1)R5,R5,#10R2,R2,#4R7,R7,1R5,0(R1)R5,R5,#10R2,R2,#4R7,R7,1R5,0(R1)ADDIR5,R5,#10ADDIR2,R2,#4SUBR7,R7,1LWR5,0(R1)ADDIR5,R5,#10ADDIR2,R2,#4SUBR7,R7,1BNEZR7,LOOPTRAP#0A:.WORD0,4,8,12,16,20,24,28,32,36B:.WORD9,8,7,6,5,4,3,2,1,0循环展开+指令调度后的

30、代码:LHIR2,(A16)&0XFFFFADDUIR2,R2,A+8LHIR3,(B16)&0XFFFFADDUIR3,R3,B&0XFFFFLWADDIADDLOOP:LWADDISUBADDILWADDISUBADDILWADDISUBADDILWADDISUBADDIBNEZTRAPR1,0(R2)R7,R0,8R1,R1,R3R5,0(R1)R2,R2,#4R7,R7,1R5,R5,#10R5,0(R1)R2,R2,#4R7,R7,1R5,R5,#10R5,0(R1)R2,R2,#4R7,R7,1R5,R5,#10R5,0(R1)R2,R2,#4R7,R7,1R5,R5,#10R7,

31、LOOP#0A:.WORD0,4,8,12,16,20,24,28,32,36B:.WORD9,8,7,6,5,4,3,2,1,0系统结构实验系统结构实验 实验三cache性能分析一、实验目的加深对Cache的基本概念、基本组织结构以及基本工作原理的理解；了解Cache的容量、相联度、块大小对Cache性能的影响；掌握降低Cache失效率的各种方法，以及这些方法对Cache性能提高的好处;理解Cache失效的产生原因以及Cache的三种失效；理解LRU与随机法的基本思想，及它们对Cache性能的影响；二、实验原理现代微机系统结构的另一重要技术是Cache。但是Cache一般位于CPU内部，即使

32、是对汇编语言程序员也是不可见的。为了直观的建立Cache技术的各种概念，形象的学习甚至于自己动手进行Cache性能分析，设计一系列有针对性的仿真实验是个很好的教学方法。SimpleScalar工具集中有专门针对Cache技术的模拟器sim-cache和sim-cheetah，正是完成这些仿真实验的理想平台。借助这两个工具，我们在系统结构课程中增设了Cache性能分析的系列仿真实验帮助学生更好的理解和掌握Cache技术。三、实验过程1基本配置情况下运行程序默认参数：-cache:dl1dl1:256:32:1:l-cache:dl2ul2:1024:64:4:l-cache:il1il1:256

33、:32:1:lbenchmarkbin.littletest-mathil1.missesil1.miss_rate23761#totalnumberofmisses0.1113#missrate(i.e.,misses/ref)benchmarksuppliedvortex.ss5122#totalnumberofmissesil1.missesil1.miss_rate0.1223#missrate(i.e.,misses/ref)benchmarkbin.littletest-fmathill.missesill.replacementsill.writebacksill.invalid

34、ationsill.miss_rateill.repl_rate112488112232totaltotaltotalnumbernumbernumbernumbermissesreplacementswritebacksirivalidations01.0620#missrate(i.e.,misses/ref)0-.0619#replacementrate(i.e.,repls/ref)2改变Cache容量对Cache性能的影响；benchmarkbin.littletest-printf-cache:il1il1:512:32:1:lillmissesill.replacementsil

35、l.writebacksill.invalidationsill.miss_rateill.repl_rate-cache:il1il1:1024:32:1:lill.missesill.replaceinentsill.writebacksill.invalidationsill.miss_rateill.repl_rate6QQ1659507a0.0331#0.032S23335224080.01290-.0124totaltotaltot日1totalnumbernumbernumbernumbermissrate(ireplacementrate(i.eafmissesofreplac

36、ementsofivritebacksofinvalidationse.,misses/ref).,repls/ref)totaltotalnumbernumbernumbernumberofmissesofreplaceiti&ntsof応讥ebacksofinvalidationse.,misses/ref)tot日.missrate(ireplacementrate(i.e.,repls/ref)-cache:il1il1:2048:32:1:lill.missesill.replacementsill.writebacksill.invalidationsill.mis_rateill

37、.repl_rate85787165tot日1totaltotalnumbernumbernumbernumberofmissesofreplacementsofwritebacksfinvalidations0.0047#missrate(i.e.,misses/ref)0.0040#replacementrate(i.e.,repls/ref)-cache:il1il1:16384:32:1:lill.missesill.replacementsill.writebacksill.invalidationsill.miss_rateill.repl_rate00.00080.0000tQt

38、altotaltot日1totalnumbernumbernumbernumberofmissesofreplacementsoflrnrritebacksofinvalidationse.,misses/ref)missrate(ireplacementrate(i.e.,repls/ref)benchmarkbin.littletest-math-cache:il1il1:512:32:1:lil1.missesil1.miss_rate-cache:il1il1.misses15565#totalnumberofmisses0.0729#missrate(i.e.,misses/ref)

39、il1:1024:32:1:l6614#totalnumberofmissesil1.miss_rate-cache:il10.0310#missrate(i.e.,misses/ref)il1:2048:32:1:lil1.missesil1.miss_rate2712#totalnumberofmisses0.0127#missrate(i.e.,misses/ref)14-cache:il1il1:16384:32:1:lil1.missesil1.miss_rate1636#totalnumberofmisses0.0077#missrate(i.e.,misses/ref)bench

40、marksuppliedvortex.ss-cache:il1il1.missesil1:512:32:1:l3241#totalnumberofmissesil1.miss_rate-cache:il10.0774#missrate(i.e.,misses/ref)il1:1024:32:1:lil1.missesil1.miss_rate-cache:il12497#totalnumberofmisses0.0596#missrate(i.e.,misses/ref)il1:2048:32:1:lil1.missesil1.miss_rate-cache:il1il1.misses1111

41、#totalnumberofmisses0.0265#missrate(i.e.,misses/ref)il1:16384:32:1:l590#totalnumberofmissesil1.miss_rate0.0141#missrate(i.e.,misses/ref)Cache容量对Cache性能的影响:Cache容量越大，失效率越低，命中率越高。系统结构实验系统结构实验 3改变Cache的相联度对Cache性能的影响；benchmarkbin.littletest-printf-cache:il1il1:256:32:1:lill.hitsillmissesill.replacement

42、sill.writebacksill.invalidationsilliniss_rateill.repl_rate1701257totalnumberfhits112488totalnumberafmisses112232并tatalnumberfreplaceitients0totalnumberafwritebacks0totalnumberofinvalidations00ZQ并missratei己.,misses/ref)0-.0CL9#replacementrate(i.e.,repls/ref)-cache:il1il1:256:32:2:lill.hitsill.missesi

43、ll.replacementsill.writebacksill.invalidationsilliuiss_rRt亡ill.repl_rate1782265totalnumber31480totalnumber30963totalnumbertotalnumbertotalnumber001“0.0171#missrate(ireplacementrmte(i.e.fhitsfmissesfreplacementsofwritebacksfinvalidations亡,misses/ref),repls/ref)-cache:il1il1:256:32:4:lill.hitsill.miss

44、esill.replaceitientsill.writebacksill.invalidationsill.miss_rateill.repl_rate1803592#totalnumberafhits4153totalnumberafmisses3135totRlnumberafreplacements0totalnumberafwritebacks0numberafinvalidationsO.0023#missrate(i.e.,misses/ref)0-.0017#replacementrate(1.e.,repls/ref)-cache:il1il1:256:32:8:lill.h

45、itsill.misseotaltotalnuitibernumberfofhitsmissesill.replaceitientsill.writebacksill.iiivalidatianstotaltotaltotalnumbernuitibernumberoffofreplacementswritebacksinvalidationsill.itiiss_rateill.repl_rate-cache:illill:256:32:64:lo.aooso.aooomissrate(i.e.,misses/ref)replacementrate(i.e.,rep

46、ls/ref)ill.hi1S1223Ototalnumberfhitsill.misses1515totalniimberofmissesill.replaceitientsill.writebackstotaltotalnumbernumberffreplacementswritebacksill.invalidatioiisill.itiiss_rateill.repl_ratenuitiberinvalidationsbenchmarkbin.littletest-math-cache:illill.missesill:256:32:l:lo.aooso.aooototalmissra

47、te(i.e.,misses/ref)replacement(i.e.,repls/ref)2376l#totalnumberofmissesil1.miss_rate0.1113#missrate(i.e.,misses/ref)-cache:il1il1:256:32:2:lil1.misses13479#totalnumberofmissesil1.miss_rate0.0631#missrate(i.e.,misses/ref)-cache:il1il1:256:32:4:lil1.misses4889#totalnumberofmissesil1.miss_rate0.0229#mi

48、ssrate(i.e.,misses/ref)-cache:il1il1:256:32:8:lil1.misses1640#totalnumberofmissesil1.miss_rate0.0077#missrate(i.e.,misses/ref)-cache:il1il1:256:32:64:lil1.misses1636#totalnumberofmissesil1.miss_rate0.0077#missrate(i.e.,misses/ref)benchmarksuppliedvortex.ss-cache:il1il1:256:32:1:lil1.missesil1.miss_r

49、ate-cache:il1il1.misses5122#totalnumberofmisses0.1223#missrate(i.e.,misses/ref)il1:256:32:2:l2575#totalnumberofmissesil1.miss_rate-cache:il10.0615#missrate(i.e.,misses/ref)il1:256:32:4:lil1.missesil1.miss_rate-cache:il1il1.misses619#totalnumberofmisses0.0148#missrate(i.e.,misses/ref)il1:256:32:8:l59

50、0#totalnumberofmissesil1.miss_rate-cache:il10.0141#missrate(i.e.,misses/ref)il1:256:32:64:lil1.misses590#totalnumberofmisses相联度对Cache性能的影响:相联度越路数越大，失效率越低，命中率越高。4改变Cache块大小对Cache性能的影响；ill.missesill.replacementsill.writebacksill.invalidationsill.miss_rateill.repl_rate123L412065totaltotaltotaltotalnumb

51、ernumbernumbernumberofmissesofreplacementsofwritebacksofinvalidationsO.0063#missrate(i.e.,misses/ref).0067#replacementrate(i.e.,repls/ref)benchmarkbin.littletest-printf-cache:il1il1:256:64:1:l-cache:dl2ul2:1024:256:4:lill.missesill.replacementsill.wtitebacksill.invali-dationsill.m.iss_rateill.repl_r

52、ate41012#totalJiumberofmisses40756井tatalnumberofreplacements#totalJinmberofwritebacks0#totalnumberofinvalidations0.0226#missrate(i.e.,misses/ref).0225#replaceitientratefi.e.,repls/ref)-cache:il1il1:256:128:1:l-cache:dl2ul2:1024:256:4:l-cache:il1il1:256:256:1:l-cache:dl2ul2:1024:256:4:lill.missesill.

53、replacementsill.writebacksill.invalidationsill.itiiss_rateill.repl_rate3731井totalnumber3510并totalnumber0tatalnumber0tatalnumber0.0021miss(iD.0019#replacesentfmissesofreplaceitientsofwritebacksofinvalidationse.,misses/ref)ate(i.e.,repls/ref)-cache:il1il1:256:2048:1:l-cache:dl2ul2:1024:2048:4:lill.mis

54、sesill.replacementsill.writebacksill.invalidationsill.miss_rateill.repl_rate37沖七毗日丄number沖totmlnumber0#totalnumber0#totalnumberofmissesofreplacemeiLtsofwritebacksofinvalidations.0000沖missi1日te(i.e.,misses/ref)0-.0000#replacementrate(i.e.,repls/ref)benchmarkbin.littletest-math-cache:il1il1:256:64:1:l

55、-cache:dl2ul2:1024:256:4:lill.missesill.replacementsillwritebacksill.invalidatiansillmiss_rateill.repl_rate1053110275totaltotaltotaltotalnumbernumbernumbernumberofofofofmissesreplacementswritebacksinvalidations0493井missratemisses/ref)D.O481#replaceitientrate(i.e.,repls/ref)-cache:il1il1:256:128:1:l-

56、cache:dl2ul2:1024:256:4:lill.missesill.replacementsill.writebacksill.invalidationsill.itiiss_rateill.repl_ratE29332729totaltotalnumbernumbernumbernumberomissesofreplacementsofwritebacksfinvalidations0.0140#missrate(i.e.,misses/ref)0128#replacementrate(i.e.,repls/ref)-cache:il1il1:256:256:1:l-cache:d

57、l2ul2:1024:256:4:lill.missesill.replacementsill.writebacksill.invalidationsill.miss_rateill.repl_rate538329totaltotalnumbernumbertotaltotalnumbernumberofmissesofreplacementsofwritebacksofinvalidations0-.0025#missrate(i.e.,misses/ref)0-.0015#replacement(i.e.,repls/ief)-cache:il1il1:256:2048:1:l-cache

58、:dl2ul2:1024:2048:4:lill.missesill.replacementsill.writebacksilliirvdi血打皿日ill.miss_rateill.repl_ra45#totalnumber#totalnumber#totalnumber井totalnumberofmissesofreplacGinGntsofwritebacksof0-.0002#missrate(i.e.,misses/ref.#replacementi1日te(i.e.,repls/ref)benchmarksuppliedvortex.ss-cache:il1il1:256:64:1:

59、l-cache:dl2ul2:1024:256:4:lill.missesill.replaceitientsill.writetjacksill.invalidatiansillmiss_rateill.repl_rate21161904totaltotaltataltotalnumbernumbernumbernumbermissesreplacementswritebacksinvalidations0505并missrateitiisses/ref)0-.O4r54#replacementrate(i.e.,repls/ref)-cache:il1il1:256:128:1:l-cac

60、he:dl2ul2:1024:256:4:lill.missesill.replacementsill.writebacksill.invalidatiansill.miss_rateill.repl_rate1034882totaltot日.tot耳.numbernumbernumbernumberofmissesofreplacementsofwritebacksofinvalidations0.02470.0211#missrmte(i.e.,misses/ref)replaceitientrate(i.e.,repls/ref)-cache:il1il1:256:256:1:l-cac