基于FPGA的智能电子抢答器的设计 (2)课件

基于FPGA的智能电子抢答器的设计报告人:XXX学号：XXXXXX指导老师:XXX毕业设计答辩毕业设计答辩课题简介：基于VHDL语言，并采用FPGA作为控制核心，设计一种四路智能电子抢答器，使其能够实现正确显示最先抢答的选手号码，对答题时间进行l00S的限时报警以及复位重新抢答的功能。具有电路简单、操作方便、灵敏可靠等优点。毕业设计答辩实施方案：利用VHDL硬件描述语言进行编程，我的这个设计主要包括七个模块：判断模块，锁存模块，转换模块，扫描模块，片选模块，定时报警模块和译码模块。编程完成后，用QuartersII软件进行编译，验证正确后再进行仿真。最后利用cyclone中的EP1C3T144C8制作成实际的系统进行测试。毕业设计答辩片选信号产生模块SEL--sel.vhdLIBRARYIEEE;USEIEEESTD_LOGIC_1164.ALL;ENTITYSELISPORT(CLK:INSTD_LOGIC;a:OUTINTEGERRANGE0TO7);ENDSEL;ARCHITECTURESEL_ARCOFSELIS

BEGINPROCESS(CLK)VARIABLEAA:INTEGERRANGE0TO7;BEGINIFCLK'EVENTANDCLK='1'THENAA:=AA+1;ENDIF;A<=AA;ENDPROCESS;ENDSEL_ARC;锁存器模块LOCKB--lockb.vhdLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYLOCKBISPORT(D1,D2,D3,D4:INSTD_LOGIC;CLK,CLR:INSTD_LOGIC;Q1,Q2,Q3,Q4,ALM:OUTSTD_LOGIC);ENDLOCKB;ARCHITECTURELOCK_ARCOFLOCKBISBEGINPROCESS(CLK)BEGINIFCLR='0'THENQ1<='0';Q2<='0';Q3<='0';Q4<='0';ALM<='0';ELSIFCLK'EVENTANDCLK='1'THENQ1<=D1;Q2<=D2;Q3<=D3;Q4<=D4;ALM<='1';ENDIF;ENDPROCESS;ENDLOCK_ARC;毕业设计答辩转换模块CH41A--ch41a..vhd

LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCH41AISPORT(D1,D2,D3,D4:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCH41A;ARCHITECTURECH41_ARCOFCH41AISBEGINPROCESS(D1,D2,D3,D4)VARIABLETMP:STD_LOGIC_VECTOR(3DOWNTO0);BEGINTMP:=D1&D2&D3&D4;CASETMPISWHEN"0111"=>Q<="0001";WHEN"1011"=>Q<="0010";WHEN"1101"=>Q<="0011";WHEN"1110"=>Q<="0100";WHENOTHERS=>Q<="1111";ENDCASE;ENDPROCESS;ENDCH41_ARC;3选1模块CH31A--ch31a.vhdLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCH31AISPORT(SEL:INSTD_LOGIC_VECTOR(2DOWNTO0);D1,D2,D3:INSTD_LOGIC_VECTOR(3DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCH31A;ARCHITECTURECH31_ARCOFCH31AIS

BEGINPROCESS(SEL,D1,D2,D3)BEGINCASESELISWHEN"000"=>Q<=D1;WHEN"001"=>Q<=D2;WHEN"111"=>Q<=D3;WHENOTHERS=>Q<="1111";ENDCASE;ENDPROCESS;ENDCH31_ARC;毕业设计答辩倒计时模块COUNT

--count.vhdLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOUNTISPORT(CLK,EN:INSTD_LOGIC;H,L:OUTSTD_LOGIC_VECTOR(3DOWNTO0);SOUND:OUTSTD_LOGIC);ENDCOUNT;ARCHITECTURECOUNT_ARCOFCOUNTISBEGINPROCESS(CLK,EN)VARIABLEHH,LL:STD_LOGIC_VECTOR(3DOWNTO0);BEGINIFCLK'EVENTANDCLK='1'THENIFEN='1'THEN;

IFLL=0ANDHH=0THENSOUND<='1';ELSIFLL=0THENLL:="1001";HH:=HH-1;ELSELL:=LL-1;ENDIF;ELSESOUND<='0';HH:="1001";LL:="1001";ENDIF;ENDIF;H<=HH;L<=LL;ENDPROCESS;ENDCOUNT_ARC毕业设计答辩抢答器系统原理图毕业设计答辩在QuartersII中对程序生成模块，连接电路图，可得到抢答器的顶层原理图。毕业设计答辩顶层原理图毕业设计答辩Feng抢答判断模块：Lockb锁存模块：毕业设计答辩Ch31a扫描模块：Ch41a显示转换模块：毕业设计答辩Count定时模块：Sel片选模块：毕业设计答辩结论本文介绍了基于FPGA的智