现代逻辑设计英文试卷B

中国计量学院20坦~201£学年第£学期《现代逻辑设计》课程考试试卷(B)开课二级学院：信息工程学院，考试时间：2014年9月16日13:30时考试形式：闭卷口、开卷口，允许带入场考生姓名：学号：专业：班级：题序—-四五/、.七八九总分得分评卷人:一、Fillintheblanks,(total20/100,2foreachblank)\1、Thebasicstnictiueofa\erilogHDLmoduleincludes、•、.\2、Theresultofexpression"10vz”isLj3、Commentin\erilogHDLbeginswithsymboltotheendoftheline.:4、Thegeneralsymbolofblockingstatementis.Thegeneralsymbolofjnon-blockingstatementis.\5、AssumedA=2'b10,B=4'bl001,thevalueof“{A,B}‘‘is,thevalueofFis.;二、Short-answerquestions,(total20/100)j1PleasesummarizethemainstepsofdigitallogicdesignusingFPGA/CPLD.(8/100)2^DescribetwobasicdesignmethodsinEDAdesign.(6/100)3、Explainthreedifferentdescriptionstyles(Structure、DataflowandBehavior)inAerilogHDL.(6/100)三、Givethedeflnitionofthevariablesandconstants,(total12/100,3foreach)1、Definea32-bitbusofwiretypenamed"data".2^Definean8-bitvariableofintegertypenamed勺”.3、Defineaparameternamed“DATAWIDTH”whichhasthevalueof16.装!4、Defineamemoiywiththewordwidthof8andmemoiysizeof32.j四、Programcomprehension(total16/100)1>PleasecoiTecttheprogramofa3-8decoderwhichhasanenablesignal"en”.;When“en”islogic1,thedecoderworksindecodingmode.(8/100)if: module74138(a,y,en);: inputa;\ inputen;; output[7:0]y;j always@(aoren)\ if(en=l)begincase(a)! 3，b000:y=8,blllllll0;: 3^001:y=8,bllllll01;竺 3，b010:y=8,blllll011;! 3，b011:y=8,bllll0111;! 3'bl00:y=8,blll01111;: 3^101:y=8,bll011111;; 3，bll0:gblOllllll;! 3'blll:疔8'b01111111;j default:7=8^11111111;\ end: else7=8^11111111;endmodule2^Thisprogramisaboutan8-bitleftshifterwliichhasasyiicliionousrst.Fillintheblanks.(8/100)moduleshifter(din,clk,rst,dout);inputdin,clk,rst;output[7:0]dout;always@(posedgeelk)beginif(rst)elsebeginendendendmodule五、Programming(total32/100)1、Designa2-1MUXindataflowstyleorbehavioralstyle.(8/100)2^Designafalling-edgetriggeredJKflip-flopwithasynchronousactive-lowreset.(12/100)3、Designahalf^adderindiffere