LatticeECP3设计的FPGA视频协议开发技术

LatticeECP3设计的FPGA视频协议开发技术本文介绍了LatticeECP3FPGA系列主要特性，LatticeECP3-35简化方框图以及LatticeECP3视频协议板主要特性，方框图和详细的电路图。Lattice公司的LatticeECP3FPGA系列能提供高性能的特性如增强的DSP架构，高速SERDES和高速源同步接口。LatticeECP3系列采用65nm技术，有149K逻辑单元和支持多达486个用户I/O，可提供多达320个18x18乘法器以及各种并行I/O标准。广泛用于批量生产的对成本和功耗敏感的有线和无线基础设备以及各种多媒体设备。LatticeECP3主要特性：

HigherLogicDensityforIncreasedSystemIntegration

•17Kto149KLUTs

•133to586I/Os

EmbeddedSERDES

•150Mbpsto3.2GbpsforGeneric8b10b,10-bitSERDES,and8-bitSERDESmodes

•DataRates230Mbpsto3.2Gbpsperchannelforallotherprotocols

•Upto16channelsperdevice:PCIExpress,SONET/SDH,Ethernet(1GbE,SGMII,XAUI),CPRI,SMPTE3GandSerialRapidIO

sysDSP™

•Fullycascadableslicearchitecture

•12to160slicesforhighperformancemultiplyandaccumulate

•Powerful54-bitALUoperations

•TimeDivisionMultiplexingMACSharing

•Roundingandtruncation

•Eachslicesupports

–Half36x36,two18x18orfour9x9multipliers

–Advanced18x36MACand18x18Multiply-Multiply-Accumulate(MMAC)operations

FlexibleMemoryResources

•Upto6.85MbitssysMEM™EmbeddedBlockRAM(EBR)

•36Kto303KbitsdistributedRAM

sysCLOCKAnalogPLLsandDLLs

•TwoDLLsanduptotenPLLsperdevice

Pre-EngineeredSourceSynchronousI/O

•DDRregistersinI/Ocells

•Dedicatedread/writelevellingfunctionality

•Dedicatedgearinglogic

•Sourcesynchronousstandardssupport

–ADC/DAC,7:1LVDS,XGMII

–HighSpeedADC/DACdevices

•DedicatedDDR/DDR2/DDR3memorywithDQSsupport

•OptionalInter-SymbolInterference(ISI)correctiononoutputs

ProgrammablesysI/O™BufferSupportsWideRangeofInterfaces

•On-chiptermination

•Optionalequalizationfilteroninputs

•LVTTLandLVCMOS33/25/18/15/12

•SSTL33/25/18/15I,II

•HSTL15IandHSTL18I,II

•PCIandDifferentialHSTL,SSTL

•LVDS,Bus-LVDS,LVPECL,RSDS,MLVDS

FlexibleDeviceConfiguration

•DedicatedbankforconfigurationI/Os

•SPIbootflashinterface

•Dual-bootimagessupported

•SlaveSPI

•TransFR™I/Oforsimplefieldupdates

•SoftErrorDetectembeddedmacro

SystemLevelSupport

•IEEE1149.1andIEEE1532compliant

•RevealLogicAnalyzer

•ORCAstraFPGAconfigurationutility

•On-chiposcillatorforinitialization&generaluse

•1.2Vcorepowersupply

LatticeECP3™系列选择指引表：

图1。LatticeECP3-35简化方框图（顶层）

LatticeECP3视频协议板

LatticeECP3VideoProtocolBoard

TheLatticeECP3™FPGAfamilyincludesmanyfeaturesforvideoapplications.Forexample,DisplayPort,SMPTEstandards(SD-SDI,HD-SDIand3G-SDI),DVB-ASI,DVIandHDMIcanbeimplementedwith16channelsofembeddedSERDES/PCS.7:1LVDSvideointerfaceslikeChannelLinkandCameraLinkcanbesupportedbythegenericDDRX2modeontheI/Opins.WhenconfiguringtoTRLVDSmode,theI/Opinsonbanks0and1canalsobeusedtoreceivetheTMDSsignalsofDVIorHDMIvideostandard.

Thisuser’sguidedescribesrevisionCoftheLatticeECP3VideoProtocolBoardfeaturingtheLatticeECP3LFE3-95E-7FN1156CFPGAdevice.Thestand-aloneevaluationPCBprovidesafunctionalplatformfordevelopmentandrapidprototypingofmanydifferentvideoapplications.

图2。LatticeECP3视频协议板外形图-Rev.C

主要特性：

•Videointerfacesforinterconnectiontovideostandardequipment

•AllowthedemonstrationofSD/HD/3G-SDI,DisplayPortandPCIExpress(x4)interfacesusingSERDESchannels

•HighspeedMezzanineconnectorconnectedtoSERDESchannelsforfutureexpansion

•AllowsthedemonstrationofLVDSvideostandards–ChannelLinkandCameraLink

•AllowscontrolofSERDESPCSregistersusingtheSerialClientInterface(ORCAstra)

•AllowsthedemonstrationofreceivingTMDSsignalsusingtheDVIinterface

•On-boardBootFlashwithSerialSPIFlashmemorydevice

•ShowsinteroperationwithhighperformanceDDR2memorycomponents

•Driver-based“run-time”deviceconfigurationcapabilityviaanORCAstraorRS232interface

•SMAsforexternalhigh-speedclock/PLLinputs

•Switches,LEDsandLCDdisplayheaderfordemopurposes

•MictorconnectorforusingLogicAnalyzerinthedebuggingphase

•Inputconnectionforlab-powersupply

•Powerconnectionsandpowersources

•ispVM™programmingsupport

•On-boardandexternalreferenceclocksources

•Varioushigh-speedlayoutstructures

•User-definedinputandoutputpoints

•Performancemonitoringviatestheaders,LEDsandswitches

图3。LatticeECP3视频协议板-Rev.C功能框图

图4。DisplayPort视频接口方框图

图5。LatticeECP3视频协议板方框图

图6。LatticeECP3视频协议板电路图-电源

图7。LatticeECP3视频协议板电路图-电源管理

图8。LatticeECP3视频协议板电路图-FPGA电源

图9。LatticeECP3视频协议板电路图-FPGA配置

图10。LatticeECP3视频协议板电路图-SERDES

图11。LatticeECP3视频协议板电路图-DDR2存储器

图12。LatticeECP3视频协议板电路图-DVVL