计算机组成原理模型机实验报告

./实验六计算机系统综合设计与实现一、实验目的1、深入理解计算机系统工作的基本原理,建立整机概念。2、融会贯通计算机组成原理课程的容,通过知识的综合运用,加深对计算机系统各模块的工作原理及相互联系的认识。3、培养科学研究的独立工作能力,取得工程设计与组装调试的实践经验。二、实验要求1、将已经设计的运算器、存储器和控制器连接,构建完整的计算机系统；2、编写一段可以实现一定功能的指令程序,进行计算机整机系统功能的验证。3、所有任务要求功能仿真和必要的验证。实验完成后,一周提交实验报告。三、实验设备PC机+QuartusⅡ10.0+FPGA<DE2-115>+TEC-8实验箱四、计算机系统〔TEC-8综合逻辑框图硬连线控制器控制信号切换电路ALUA端口B端口CZR0R1R2R3IRPCAR双端口RAMDBUS五、实验任务1、将实验二的运算器、实验三的存储器和实验五的控制器连接,构建完整的计算机系统；2、计算机整机系统功能测试,进行功能仿真和时序仿真并在DE2-115上验证。〔1根据指令系统,编写一段可以实现一定功能的程序,要求：有一个合理的运算功能和逻辑关系；指令数量：不少于8条；指令类型：停机、跳转、RR、读存、写存、算术和逻辑运算；〔2将指令程序手工汇编成二进制代码；〔3理论上设置寄存器的初值,并计算程序执行后的结果；〔4将指令程序的二进制代码存入存储器RAM中；〔5将需要的运算数据初值存入寄存器R0-R3中；〔6进行程序连续运行的功能仿真和时序仿真,将仿真运算结果与理论计算结果进行比较。六、实验步骤实验电路图子模块〔1tri_74244tri74244.vmoduletri_74244<en,Din,Dout>;inputen;wireen;input[7:0]Din;wire[7:0]Din;output[7:0]Dout;reg[7:0]Dout;always<enorDin>beginif<en>Dout<=Din;elseDout<=8'bzzzzzzzz;endendmodule`timescale1ps/1psmoduletri_74244_vlg_tst<>;regeachvec;reg[7:0]Din;regen;wire[7:0]Dout;tri74244.vt`timescale1ps/1psmoduletri_74244_vlg_tst<>;regeachvec;reg[7:0]Din;regen;wire[7:0]Dout;tri_74244i1< .Din<Din>, .Dout<Dout>, .en<en>>;integeri;initialbegini=0;Din=8'b00000000;en=0;en=1;#30en=0;#40en=1;endinitialbeginfor<i=0;i<10;i=i+1>begin#10Din=i;endendendmoduletri74244功能仿真〔2ALUALU.bdfmodolue_74181 使用quartus库中的74181模块转换为verilog文件即可de2_4de2_4.vmodulede2_4<en,in,out>;input[2:1]in;inputen;output[4:1]out;reg[4:1]out;always<enorin>if<en>case<in>2'b00:out=4'b0001;2'b01:out=4'b0010;2'b10:out=4'b0100;2'b11:out=4'b1000;default:out=4'b0000;endcaseelseout=4'b0000;endmodulede2_4.vt`timescale1ns/1psmodulede2_4_vlg_tst<>;regeachvec;regen;reg[2:1]in;wire[4:1]out;de2_4i1< .en<en>, .in<in>, .out<out>>;initialbeginen=0;endinitialbegin#10en=1;endinitialbegin#5in=2'b00;#15in=2'b01;#15in=2'b10;#15in=2'b11;#40$finish;endinitial$monitor<$time,,,"en=%bin=%bout=%b",en,in,out>;endmodulereg8reg8.vmodulereg8<T3,DOUT,D>;inputT3;wireT3;input[7:0]D;wire[7:0]D;output[7:0]DOUT;reg[7:0]DOUT;always<posedgeT3>beginDOUT<=D;endendmodulereg8.vt`timescale1ps/1psmodulereg8_vlg_tst<>;regeachvec;reg[7:0]D;regT3;wire[7:0]DOUT;reg8i1< .D<D>, .DOUT<DOUT>, .T3<T3>>;integeri;initialbeginT3=0;D=8'd0;endalwaysbegin#5T3=~T3;endinitialbeginfor<i=0;i<11;i=i+1>begin#10D=i;endendendmodulemux4_1mux4_1.vmodulemux4_1<d1,d2,d3,d4,se1,se2,dout>;input[7:0]d1;input[7:0]d2;input[7:0]d3;input[7:0]d4;inputse1;inputse2;outputdout;reg[7:0]dout;always<d1ord2ord3ord4orse1orse2>case<{se2,se1}>2'b00:dout=d1;2'b01:dout=d2;2'b10:dout=d3;2'b11:dout=d4;endcaseendmodulemux4_1.vt`timescale1ps/1psmodulemux4_1_vlg_tst<>;regeachvec;reg[7:0]d1;reg[7:0]d2;reg[7:0]d3;reg[7:0]d4;regse1;regse2;wire[7:0]dout;mux4_1i1< .d1<d1>, .d2<d2>, .d3<d3>, .d4<d4>, .dout<dout>, .se1<se1>, .se2<se2>>;integeri,j;initialbegin#10d1=8'b00000001;d2=8'b00000010;d3=8'b00000011;d4=8'b00000100;endinitialbegin#5while<1>for<i=0;i<2;i=i+1>for<j=0;j<2;j=j+1>begin#5se2=i;se1=j;endendendmoduleALU逻辑电路图逻辑功能表〔1写寄存器〔例如：向通用寄存器R0-R3分别写入数据55H/AAH/03H/04HT3RDDRWSBUSABUSDBUS[7..0]功能<写R>↑0011055H55H→R0↑01110AAHAAH→R1↑1011003H03H→R2↑1111004H04H→R3〔2选择将R0送74181的A端口,R1送B端口,进行算术功能验算MCnS[3..0]RDRSDRWSBUSABUSDBUS[7..0]0100000001001550100010001001ff……011111000100154〔3选择将R0送74181的A端口,R1送B端口,进行逻辑功能验算MCnS[3..0]RDRSDRWSBUSABUSDBUS[7..0]1000000001001AA100001000100100……101111000100155当A=55H,B=AAH,S=0000~1111,M=0,CIN=1时仿真测试文件及功能仿真波形`timescale1ns/1psmodulealu_vlg_tst<>;regT3;regSBUS;regDRW;regABUS;regLDC;regCIN;regM;reg[1:0]RD;reg[1:0]RS;reg[3:0]S;reg[7:0]SD;wire[7:0]DBUS;wireC;alui1< .ABUS<ABUS>, .C<C>, .CIN<CIN>, .DBUS<DBUS>, .DRW<DRW>, .LDC<LDC>, .M<M>, .RD<RD>, .RS<RS>, .S<S>, .SBUS<SBUS>, .SD<SD>, .T3<T3>>;initialbeginT3=0;SBUS=1;DRW=1;ABUS=0;RD=2'b00;SD=8'b01010101;#10RD=2'b01;SD=8'b10101010;#10RD=2'b10;SD=8'b00000011;#10RD=2'b11;SD=8'b00000100;#10RD=2'b00;RS=2'b01;SBUS=0;DRW=0;ABUS=1;CIN=1;LDC=1;M=0;endalwaysbegin#5T3=~T3;endintegeri;initialbegin#40S=4'b0000;for<i=1;i<16;i=i+1>#10S=i;endinitial$monitor<$time,,,"M=%bS=%bCIN=%bSD=%hDBUS=%hC=%b",M,S,CIN,SD,DBUS,C>;endmodule指令ADDR0,R1〔R0+R1→R0的仿真测试文件及功能仿真波形`timescale1ns/1psmodulealu_vlg_tst<>;regT3;regSBUS;regDRW;regABUS;regLDC;regCIN;regM;reg[1:0]RD;reg[1:0]RS;reg[3:0]S;reg[7:0]SD;wire[7:0]DBUS;wireC;alui1< .ABUS<ABUS>, .C<C>, .CIN<CIN>, .DBUS<DBUS>, .DRW<DRW>, .LDC<LDC>, .M<M>, .RD<RD>, .RS<RS>, .S<S>, .SBUS<SBUS>, .SD<SD>, .T3<T3>>;initialforkT3=0;SBUS=1;DRW=1;ABUS=0;RD=2'b00;SD=8'b00000111;#10RD=2'b01;#10SD=8'b00000001;#20RD=2'b00;#20RS=2'b01;#20SBUS=0;#20DRW=0;#20ABUS=1;#20CIN=1;#20LDC=1;#20M=0;#20S=4'b1001;#30RD=2'b00;#30DRW=1;#40DRW=0;joinalwaysbegin#5T3=~T3;endendmodule00nsDBUS=07HT3上升沿到来〔5ns时数据07H被写R010nsDBUS=01HT3上升沿到来〔15ns时数据01H被写R120nsDBUS=R0+R1=07+01=08H30nsT3上升沿到来〔35ns时DBUS数据08H被写R0,因此DBUS=R0+R1=08H+01H=09H〔说明实现了R0+R1→R0注意：此时M=0,S=1001,CIN=1〔相当于C0=0,实现算术运算A+B指令SUBR0,R1〔R0-R1→R0的仿真测试文件及功能仿真波形`timescale1ns/1psmodulealu_vlg_tst<>;regT3;regSBUS;regDRW;regABUS;regLDC;regCIN;regM;reg[1:0]RD;reg[1:0]RS;reg[3:0]S;reg[7:0]SD;wire[7:0]DBUS;wireC;alui1< .ABUS<ABUS>, .C<C>, .CIN<CIN>, .DBUS<DBUS>, .DRW<DRW>, .LDC<LDC>, .M<M>, .RD<RD>, .RS<RS>, .S<S>, .SBUS<SBUS>, .SD<SD>, .T3<T3>>;initialforkT3=0;SBUS=1;DRW=1;ABUS=0;RD=2'b00;SD=8'b00000111;#10RD=2'b01;#10SD=8'b00000001;#20RD=2'b00;#20RS=2'b01;#20SBUS=0;#20DRW=0;#20ABUS=1;#20CIN=0;#20LDC=1;#20M=0;#20S=4'b0110;#30RD=2'b00;#30DRW=1;#40DRW=0;joinalwaysbegin#5T3=~T3;endendmodule00nsDBUS=03HT3上升沿到来〔5ns时数据07H被写R010nsDBUS=01HT3上升沿到来〔15ns时数据01H被写R120nsDBUS=R0-R1=07-01=06H30nsT3上升沿到来〔35ns时DBUS数据06H被写R0,因此DBUS=R0-R1=06H-01H=05H〔说明实现了R0-R1→R0注意：此时M=0,S=0110,实现算术运算A-B-1,设置CIN=0〔相当于C0=1,让进位C0=1,因此实现运算<A-B-1>+1=A-B指令ANDR0,R1〔R0&R1→R0的仿真测试文件及功能仿真波形`timescale1ns/1psmodulealu_vlg_tst<>;regT3;regSBUS;regDRW;regABUS;regLDC;regCIN;regM;reg[1:0]RD;reg[1:0]RS;reg[3:0]S;reg[7:0]SD;wire[7:0]DBUS;wireC;alui1< .ABUS<ABUS>, .C<C>, .CIN<CIN>, .DBUS<DBUS>, .DRW<DRW>, .LDC<LDC>, .M<M>, .RD<RD>, .RS<RS>, .S<S>, .SBUS<SBUS>, .SD<SD>, .T3<T3>>;initialforkT3=0;SBUS=1;DRW=1;ABUS=0;RD=2'b00;SD=8'b00000111;#10RD=2'b01;#10SD=8'b00001001;#20RD=2'b00;#20RS=2'b01;#20SBUS=0;#20DRW=0;#20ABUS=1;#20CIN=1;#20LDC=1;#20M=1;#20S=4'b1011;#30RD=2'b00;#30DRW=1;#38S=4'b0000;#40DRW=0;joinalwaysbegin#5T3=~T3;endendmodule00nsDBUS=00000111T3上升沿到来〔5ns时数据00000111被写R010nsDBUS=00001001T3上升沿到来〔15ns时数据00001001被写R120nsDBUS=R0&R1=0000000130nsDRW=1T3上升沿到来〔35ns时DBUS数据00000001被写R0,38nsM=1,S=0000DBUS=R0&R1==11111110H实现了求反运算〔说明已经实现了R0&R1→R0〔3RAM4RAM4.bdfcnt256cnt256.vmodulet256<Q,DATA,LDN,reset,clk>;output[7:0]Q;input[7:0]DATA;inputLDN,reset,clk;reg[7:0]Q;always<posedgeclkornegedgereset>//clk上升沿触发beginif<!reset>//异步清零,低电平有效Q<=8'b0;elseif<!LDN>Q<=DATA;//同步置数,低电平有效 elseQ<=Q+1;//计数endendmodulecnt256.vt`timescale1ns/1psmodulet256_vlg_tst<>;reg[7:0]DATA;regLDN;regclk;regreset;wire[7:0]Q;cnt256i1< .DATA<DATA>, .LDN<LDN>, .Q<Q>, .clk<clk>, .reset<reset>>;initialbeginDATA=1'hA;clk=0;reset=1;LDN=1;DATA=8'd00010010;#20reset=0;#40reset=1;#260LDN=0;#80LDN=1;endalwaysbegin#20clk=~clk;endendmoduleasdf 利用宏功能模块先生成单端口存储器,再用两单端口存储器进行连接生成双端口存储器RAM4仿真测试逻辑图双端口逻辑功能表〔1从左端口写存储器〔在01H单元中写入数据11H〔右端口为只读端口T2T3MEMWSBUSLARLPCMBUSCLR_ARINCPCINCSD[7..0]功能x↑011001000101H→AR↑x110001001111H→<01H>〔地址线和数据线分时复用技术,先送地址,再送数据用同样方法在02H中写入22H〔2从左端口读存储器〔从01H中读出数据11H〔右端口为只读端口T2T3MEMWSBUSLARLPCMBUSCLR_ARINCPCINCSD[7..0]功能x↑011001000101H→AR↑x00001100xx<01H>→DBUS〔地址线和数据线分时复用技术,先送地址,再送数据用同样方法读出02H中的22H〔3从右端口读存储器〔从01H中读出数据11H〔右端口为只读端口T2T3MEMWSBUSLARLPCMBUSCLR_ARINCPCINCSD[7..0]功能x↑010101000101H→PC↑x00001100xx<01H>→INS〔地址线和数据线分时复用技术,先送地址,再送数据用同样方法读出02H中的22H〔4AR自动加1读存储器〔从左端口连续读存储器T2T3MEMWSBUSLARLPCMBUSCLR_ARINCPCINCSD[7..0]功能↑x00001110XXM→DBUS〔5PC自动加1读存储器〔从右端口连续读存储器T2T3MEMWSBUSLARLPCMBUSCLR_ARINCPCINCSD[7..0]功能↑x00000101XXM→INS〔4UCU_ir_1UCU_ir_1.bdfram64_40rom64_40.vmodulerom64_40< addr, q>; input [5:0]addr; output [39:0]q; reg[39:0]q; always<addr[5]oraddr[4]oraddr[3]oraddr[2]oraddr[1]oraddr[0]> begin case<{addr[5],addr[4],addr[3],addr[2],addr[1],addr[0]}> 6'h00:q<=40'h0c00000041; 6'h01:q<=40'h00000410a0; 6'h02:q<=40'h4010034002; 6'h03:q<=40'h4010028002; 6'h04:q<=40'h4020024004; 6'h05:q<=40'h4010028004; 6'h06:q<=40'h6c00020000; 6'h07:q<=40'h4400020006; 6'h08:q<=40'h501002080a; 6'h09:q<=40'h4410020808; 6'h0a:q<=40'h641002080c; 6'h0b:q<=40'h4410020815; 6'h0c:q<=40'h7810020800; 6'h0d:q<=40'h401002a01a; 6'h0e:q<=40'h0020000c01; 6'h0f:q<=40'h4410020832; 6'h10:q<=40'h000e810401; 6'h11:q<=40'h0180020014; 6'h12:q<=40'h0000000401; 6'h13:q<=40'h8000000401; 6'h14:q<=40'h0010002001; 6'h15:q<=40'h5010020816; 6'h16:q<=40'h440a7a0017; 6'h17:q<=40'h44099a0018; 6'h18:q<=40'h440eca0019; 6'h19:q<=40'h440f8a0000; 6'h1a:q<=40'h401003401b; 6'h1b:q<=40'h401003501c; 6'h1c:q<=40'h401003501d; 6'h1d:q<=40'h401002a01f; 6'h1e:q<=40'h0000000000; 6'h1f:q<=40'h4020025030; 6'h20:q<=40'h0000000000; 6'h21:q<=40'h000a780c01; 6'h22:q<=40'h0009980c01; 6'h23:q<=40'h000ec80c01; 6'h24:q<=40'h0008180c01; 6'h25:q<=40'h000e80800e; 6'h26:q<=40'h000fc08010; 6'h27:q<=40'h0000000112; 6'h28:q<=40'h0000000212; 6'h29:q<=40'h000fc02401; 6'h2a:q<=40'h000e800401; 6'h2b:q<=40'h0040002401; 6'h2c:q<=40'h0100000001; 6'h2d:q<=40'h0200000001; 6'h2e:q<=40'h0000020401; 6'h2f:q<=40'h0000000000; 6'h30:q<=40'h4020025031; 6'h31:q<=40'h4020020000; 6'h32:q<=40'h5010020833; 6'h33:q<=40'h64100c0834; 6'h34:q<=40'h7810020835; 6'h35:q<=40'h4c1002a036; 6'h36:q<=40'h400e834037; 6'h37:q<=40'h440e835038; 6'h38:q<=40'h480e835039; 6'h39:q<=40'h4c0e83503a; 6'h3a:q<=40'h4c1002803b; 6'h3b:q<=40'h702002483c; 6'h3c:q<=40'h6c2002483d; 6'h3d:q<=40'h582002483e; 6'h3e:q<=40'h4420024800; 6'h3f:q<=40'h0000000000; default:beginend endcase end endmodulerom64_40.vt`timescale1ns/1psmodulerom64_40_vlg_tst<>;reg[5:0]addr;wire[39:0]q;rom64_40i1< .addr<addr>, .q<q>>;integeri;initialbeginfor<i=0;i<64;i=i+1>begin#50addr=i;endendendmodulereg6reg6.vmodulereg6<CLK,DOUT,D,CLR_>;inputCLK;wireCLK;input[5:0]D;wire[5:0]D;inputCLR_;wireCLR_;output[5:0]DOUT;reg[5:0]DOUT;always<negedgeCLKornegedgeCLR_>beginif<CLR_==0>DOUT<=6'd0;elseDOUT<=D;endendmodulereg6.vt`timescale1ps/1psmodulereg6_vlg_tst<>;regCLK;regCLR_;reg[5:0]D;wire[5:0]DOUT;reg6i1< .CLK<CLK>, .CLR_<CLR_>, .D<D>, .DOUT<DOUT>>;integeri;initialbeginCLK=0;D=6'd1;CLR_=1;#10CLR_=0;#10CLR_=1;#30D=6'd2;endalwaysbegin#20CLK=~CLK;endinitialbegin#50for<i=3;i<15;i=i+1>begin#40D=i;endendendmoduleaddrtranaddrtran.bdfaddrtran.vt`timescale1ps/1psmoduleaddrtran_vlg_tst<>;regeachvec;regC;regINT;reg[7:4]IR;reg[5:0]NuA;reg[4:0]P;regSWA;regSWB;regSWC;regZ;wire[5:0]uA;addrtrani1< .C<C>, .\INT<INT>, .IR<IR>, .NuA<NuA>, .P<P>, .SWA<SWA>, .SWB<SWB>, .SWC<SWC>, .uA<uA>, .Z<Z>>;initialbeginINT=0;C=0;Z=0;P=5'd1;NuA=2'o01;SWC=0;SWB=0;SWA=0;#20SWA=1;#20SWA=0;SWB=1;#20SWA=1;#20SWA=0;SWB=0;SWC=1;#20SWC=0;P=5'd2;NuA=6'd010000;endintegeri;initial#80beginfor<i=0;i<16;i=i+1>#20IR=i;endendmodulemicro_controller.bdfMicro_controller.vt`timescale1ns/1psmodulemicro_controller_vlg_tst<>;regeachvec;regC;regCLR_;regINT;reg[7:4]IR;regSWA;regSWB;regSWC;regT3;regZ;wireABUS;wireARINC;wireCIN;wire[39:0]CM;wireDRW;wireIABUS;wireINTDI;wireINTEN;wireLAR;wireLDC;wireLDZ;wireLIAR;wireLIR;wireLPC;wireM;wireMBUS;wireMEMW;wirePCADD;wirePCINC;wire[3:0]S;wireSBUS;wire[3:0]SEL;wireSELCTL;wireSTOP;micro_controlleri1< .ABUS<ABUS>, .ARINC<ARINC>, .C<C>, .CIN<CIN>, .CLR_<CLR_>, .CM<CM>, .DRW<DRW>, .IABUS<IABUS>, .\INT<INT>, .INTDI<INTDI>, .INTEN<INTEN>, .IR<IR>, .LAR<LAR>, .LDC<LDC>, .LDZ<LDZ>, .LIAR<LIAR>, .LIR<LIR>, .LPC<LPC>, .M<M>, .MBUS<MBUS>, .MEMW<MEMW>, .PCADD<PCADD>, .PCINC<PCINC>, .S<S>, .SBUS<SBUS>, .SEL<SEL>, .SELCTL<SELCTL>, .STOP<STOP>, .SWA<SWA>, .SWB<SWB>, .SWC<SWC>, .T3<T3>, .Z<Z>>;initialbeginCLR_=0;T3=0;#30Z=0;C=0;INT=0;CLR_=1;SWC=0;SWB=0;SWA=0;endalwaysbegin#20T3=~T3;endintegeri;initialbeginfor<i=1;i<16;i=i+1>begin#80IR=i;endendendmodulereg8 同ALU模块中的reg8mux2_1mux2_1.vmodulemux2_1<d0,d1,sel,dout>;input[3:0]d0;input[3:0]d1;inputsel;outputdout;reg[3:0]dout;always<d0ord1orsel>case<sel>1'b0:dout=d0;1'b1:dout=d1;endcaseendmodulemux2_1.vt`timescale1ps/1psmodulemux2_1_vlg_tst<>;regeachvec;reg[3:0]d0;reg[3:0]d1;regsel;wire[3:0]dout;mux2_1i1< .d0<d0>, .d1<d1>, .dout<dout>, .sel<sel>>;initialbegind0=4'b0001;d1=4'b1110;endintegeri;initialwhile<1>beginfor<i=0;i<2;i=i+1>begin#50sel=i;endendendmoduleUCU_ir_1仿真测试ADD-SUB-AND-INC指令,2个CPU周期Testbench`timescale1ns/1psmoduleucu_ir_vlg_tst<>;regeachvec;regC;regCLR_;reg[7:0]INS;regINT;regSWA;regSWB;regSWC;regT3;regZ;wireABUS;wireARINC;wireCIN;wire[39:0]CM;wireDRW;wireIABUS;wireINTDI;wireINTEN;wireLAR;wireLDC;wireLDZ;wireLIAR;wireLIR;wireLPC;wireM;wireMBUS;wireMEMW;wirePCADD;wirePCINC;wire[1:0]RD;wire[1:0]RS;wire[3:0]S;wireSBUS;wireSTOP;ucu_iri1< .ABUS<ABUS>, .ARINC<ARINC>, .C<C>, .CIN<CIN>, .CLR_<CLR_>, .CM<CM>, .DRW<DRW>, .IABUS<IABUS>, .INS<INS>, .\INT<INT>, .INTDI<INTDI>, .INTEN<INTEN>, .LAR<LAR>, .LDC<LDC>, .LDZ<LDZ>, .LIAR<LIAR>, .LIR<LIR>, .LPC<LPC>, .M<M>, .MBUS<MBUS>, .MEMW<MEMW>, .PCADD<PCADD>, .PCINC<PCINC>, .RD<RD>, .RS<RS>, .S<S>, .SBUS<SBUS>, .STOP<STOP>, .SWA<SWA>, .SWB<SWB>, .SWC<SWC>, .T3<T3>, .Z<Z>>;initialbeginCLR_=0;T3=1;#30CLR_=1;Z=0;C=0;INT=0;SWC=0;SWB=0;SWA=0;endalwaysbegin#10T3=0;#20T3=1;endintegeri;initialbegin#40INS=8'b00010001;for<i=33;i<255;i=i+16>begin#60INS=i;endendendmoduleLD-ST-JC指令,3个CPU周期Testbench`timescale1ns/1psmoduleucu_ir_vlg_tst<>;regeachvec;regC;regCLR_;reg[7:0]INS;regINT;regSWA;regSWB;regSWC;regT3;regZ;wireABUS;wireARINC;wireCIN;wire[39:0]CM;wireDRW;wireIABUS;wireINTDI;wireINTEN;wireLAR;wireLDC;wireLDZ;wireLIAR;wireLIR;wireLPC;wireM;wireMBUS;wireMEMW;wirePCADD;wirePCINC;wire[1:0]RD;wire[1:0]RS;wire[3:0]S;wireSBUS;wireSTOP;ucu_iri1< .ABUS<ABUS>, .ARINC<ARINC>, .C<C>, .CIN<CIN>, .CLR_<CLR_>, .CM<CM>, .DRW<DRW>, .IABUS<IABUS>, .INS<INS>, .\INT<INT>, .INTDI<INTDI>, .INTEN<INTEN>, .LAR<LAR>, .LDC<LDC>, .LDZ<LDZ>, .LIAR<LIAR>, .LIR<LIR>, .LPC<LPC>, .M<M>, .MBUS<MBUS>, .MEMW<MEMW>, .PCADD<PCADD>, .PCINC<PCINC>, .RD<RD>, .RS<RS>, .S<S>, .SBUS<SBUS>, .STOP<STOP>, .SWA<SWA>, .SWB<SWB>, .SWC<SWC>, .T3<T3>, .Z<Z>>;initialbeginCLR_=0;T3=1;Z=0;C=0;INT=0;SWC=0;SWB=0;SWA=0;#30CLR_=1;endalwaysbegin#10T3=0;#20T3=1;endintegeri;initialbegin#40INS=8'b01011110;for<i=110;i<111;i=i+16>begin#90INS=i;endfor<i=112;i<225;i=i+16>begin#90INS=i;endendendmoduleJZ-JMP-OUT-STP指令Testbench`timescale1ns/1psmoduleucu_ir_vlg_tst<>;regeachvec;regC;regCLR_;reg[7:0]INS;regINT;regSWA;regSWB;regSWC;regT3;regZ;wireABUS;wireARINC;wireCIN;wire[39:0]CM;wireDRW;wireIABUS;wireINTDI;wireINTEN;wireLAR;wireLDC;wireLDZ;wireLIAR;wireLIR;wireLPC;wireM;wireMBUS;wireMEMW;wirePCADD;wirePCINC;wire[1:0]RD;wire[1:0]RS;wire[3:0]S;wireSBUS;wireSTOP;ucu_iri1< .ABUS<ABUS>, .ARINC<ARINC>, .C<C>, .CIN<CIN>, .CLR_<CLR_>, .CM<CM>, .DRW<DRW>, .I