BCD七段显示译码器的设计报告

实验二、BCD七段显示译码器的设计实验目的学习利用VHDL语言设计BCD七段显示译码器的方法，掌握BCD七段显示译码器的设计思路：掌握软件工具的使用方法。实验原理bcd七段显示译码器真值表SEQbcd七段显示译码器真值表\*ARABIC1输入输出数字A3A2A1A0YaYbYcYdYeYfYg字形00000111111001000101100001200101101101230011111100134010001100114501011011011560110101111167011111100107810001111111891001111101191010101110111A1110110011111B1211001001110C1311010111101D1411101001111E1511111000111F实验内容1.用VHDL语言设计BCD七段显示译码器，进行编译、波形仿真及器件编程。〔代码一详见附录〕产生仿真波形如下：BCD七段显示译码器仿真SEQBCD七段显示译码器仿真\*ARABIC1分析：问：给定的代码驱动的是共阴极还是共阳极的七段数码管显示器？由BCD七段显示译码器真值表可知是共阴极七段数码管显示器。2.用VHDL语言设计3-8译码器，进行编译、波形仿真及器件编程。〔代码二详见附录〕产生仿真波形如下：3-8译码器仿真SEQ3-8译码器仿真\*ARABIC1四、实验心得在实验中，通过BCD七段显示译码器真值表真值表得到BCD七段显示译码器case代码。同理通过8-3译码器真值表修改BCD七段显示译码器case代码得到8-3译码器case代码。附录代码一〔BCD七段显示译码器代码〕：libraryieee;useieee.std_logic_1164.all;entitybcdymisport(a:instd_logic_vector(3downto0);y:outstd_logic_vector(6downto0));endbcdym;architecturezhangofbcdymisbeginprocess(a)begincaseaiswhen"0000"=>y<="0111111";when"0001"=>y<="0000110";when"0010"=>y<="1011011";when"0011"=>y<="1001111";when"0100"=>y<="1100110";when"0101"=>y<="1101101";when"0110"=>y<="1111101";when"0111"=>y<="0100111";when"1000"=>y<="1111111";when"1001"=>y<="1101111";when"1010"=>y<="1110111";when"1011"=>y<="1111100";when"1100"=>y<="0111001";when"1101"=>y<="1011110";when"1110"=>y<="1111001";whenothers=>y<="1110001";endcase;endprocess;endzhang;代码二〔8-3译码器代码〕：libraryieee;useieee.std_logic_1164.all;entitybm3_8isport(a:instd_logic_vector(0to2);b:outstd_logic_vector(0to7));endbm3_8;architecturezhangofbm3_8isbeginprocess(a)begincaseaiswhen"000"=>b<="00000001";when"001"=>b<="00000010";when"010"=>b<="00000100";when"011"=>b<="00001000";when"100"=>b<="00010000";when"101"=>b<="00100000";