EDA技术及应用试卷D含答案

1《EDA技术与应用》试卷D一、填空题（每题2分，共10分）A、IEEEB、STDC、WORKD、PACKAGEA、INB、OUTC、INOUTD、BUFFER文档来源为:从网络收集整理.word版本可编辑.欢迎下载支持.USEIEEE.STD_LOGIC_1164.ALL;**PORT(d:IN;y:OUTSTD_LOGIC_VECTOR(2DOWNTO0));**ARCHITECTUREbehOFencoderISBEGINIFd(7)=’0’IFd(7)=’0’ELSIFELSIFELSIFELSIFELSIFELSIFELSIFELSIFELSIFELSIFELSIFELSIF2Endprocess;ENDbeh;USEIEEE.STD_LOGIC_1164.ALL;PORT(d,clk,clrn,prn,ena:instd_logic;PROCESS(clk,prn,clrn,ena,d)BEGINIFprn='0'THENq<='1';**ELSIFclrn='0'THENq<='0';**ELSIFclk'eventANDclk='1'THEN**ENDPROCESS;文档来源为:从网络收集整理.word版本可编辑.欢迎下载支持.Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Port(c:instd_logic;A,b:instd_logic_vector(3downto0);S:outstd_logic_vector(3downto0);;ArchitectureaofsubSignala1,a2,a3:std_logic_vector(4downto0);BeginProcessBeginA3<=a1+a2;**A3<=a1-a2;**;;Endprocess;3USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux41ISPORT(s1,s2:INSTD_LOGIC;**ENDENTITYmux41;ARCHITECTUREactivOFmux41ISBEGIN;PROCESS(s,a,b,c,d)BEGINWHENWHENWHENWHENWHEN;ENDPROCESS;**文档来源为:从网络收集整理.word版本可编辑.欢迎下载支持.4《EDA技术与应用》试卷D答案一、填空题（每题2分，共10分）A、IEEEB、STDC、WORKD、PACKAGEA、INB、OUTC、INOUTD、BUFFER4、一个设计实体可以拥有一个或多个（B）文档来源为:从网络收集整理.word版本可编辑.欢迎下载支持.USEIEEE.STD_LOGIC_1164.ALL;**PORT(d:INSTD_LOGIC_VECTOR(7DOWNTO0);y:OUTSTD_LOGIC_VECTOR(2DOWNTO0));**ARCHITECTUREbehOFencoderISBEGINProcess(d)beginIFd(7)=’0’IFd(7)=’0’ELSIFELSIFELSIFELSIFELSIFELSIFELSIFELSIFELSIFELSIFELSIFELSIF5Endprocess;ENDbeh;USEIEEE.STD_LOGIC_1164.ALL;PORT(d,clk,clrn,prn,ena:instd_logic;STD_LOGICBEGINPROCESS(clk,prn,clrn,ena,d)BEGINIFprn='0'THENq<='1';**ELSIFclrn='0'THENq<='0';**ELSIFclk'eventANDclk='1'THEN**ENDPROCESS;文档来源为:从网络收集整理.word版本可编辑.欢迎下载支持.Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Port(c:instd_logic;A,b:instd_logic_vector(3downto0);S:outstd_logic_vector(3downto0);ArchitectureaofsubSignala1,a2,a3:std_logic_vector(4downto0);BeginProcessBeginA3<=a1+a2;**A3<=a1-a2;**S<=a3(3downto0);Co<=a3(4);Endprocess;6USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux41ISPORT(s1,s2:INSTD_LOGIC;**ENDENTITYmux41;ARCHITECTUREactivOFmux41ISSIGNALs:STD_L