QuartusII时序约束方法

QuartusII时序约束方法第1页，共222页。QuartusII时序约束方法第2页，共222页。常见术语的中文翻译Tsetup:建立时间Thold：保持时间Skew：传输时差,时钟歪斜Slack：余量Fmax：最大频率Inputmaximumdelay：输入最大延时Inputminimumdelay：输入最小延时Outputmaximumdelay：输出最大延时Outputminimumdelay：输出最小延时Maxdelay：最大延时MinDelay：最小延时Recoverytime：恢复时间Removaltime：移去时间Jitter：抖动第3页，共222页。TimeQuestAgendaIntroductiontoTimeQuestTimeQuestterminologyreviewUsingTimeQuestExampleApplication第4页，共222页。TimeQuestTimingAnalyzerNewtimingengineinQuartusIIProvidetiminganalysissolutionmeetingrequirementsofallusersFPGAdesignbackgroundASICdesignbackgroundEasy-to-useinterfaceStandardreporting&constraintterminologyScriptingemphasis第5页，共222页。TimeQuestTimingAnalyzer(cont.)Moreaccurateanalysisrise/falldelaysSDCSupportMoreadvanced&standardizedconstraintmethodologyEasilysupportsmorecomplexdesignsandanalysisComplexclockingschemesSource-synchronousdesigns第6页，共222页。ValidatingPerformancewiththeTimeQuestStaticTimingAnalyzerTimeQuestTerminologyReview第7页，共222页。TimeQuestTerminologyReviewLaunch&latchedgesArrivaltimevs.requiredtimeSetup&holdanalysisSlackSDCterminology第8页，共222页。Path&AnalysisTypesThreetypesofPaths:ClockPathsDataPathAsynchronousPaths*ClockPathsAsyncPathDataPathAsyncPathDQCLRPREDQCLRPRETwotypesofAnalysis:Synchronous –clock&datapathsAsynchronous* –clock&asyncpaths*Asynchronousreferstosignalsfeedingtheasynchronouscontrolportsoftheregisters第9页，共222页。Setup&HoldSetup: Theminimumtimedatasignalmustbestable BEFOREclockedgeHold: Theminimumtimedatasignalmustbestable AFTERclockedgeDQCLRPRECLKThValidDATATsuCLKDATATogether,thesetuptimeandholdtimeformaDataRequiredWindow,thetimearoundaclockedgeinwhichdatamustbestable.第10页，共222页。Launch&LatchEdgesCLKLaunchEdgeLatchEdgeDataValidDATALaunchEdge: theedgewhich“launches”thedatafromsourceregisterLatchEdge: theedgewhich“latches”thedataatdestinationregister(withrespecttothelaunchedge,typically1cycle)第11页，共222页。Launch&LatchEdgesLaunchEdge:Clockedgethatactivatesthesourceregisterinaregister-to-registerpathLatchEdge:ClockedgethatactivatesthedestinationregisterBACLKACLKBCLKACLKBTherelationshipbetweentheedgesisderivedfromtheuser-definedclocksettings第12页，共222页。DataArrivalTimeThetimefordatatoarriveataregister’sDinputDataArrivalTime=launchedge+Tclk1+μTco+TdataLaunchEdge第13页，共222页。ClockArrivalTimeThetimeforclocktoarriveataregister’sclockinputClockArrivalTime=latchedge+Tclk2

LatchEdge第14页，共222页。DataRequiredTime-SetupTimesignalmustarriveatdestinationregistertobeproperlysampledDataRequiredTime=ClockArrivalTime–μTsu

LatchEdge第15页，共222页。DataRequiredTime-HoldDataRequiredTime=ClockArrivalTime+μTh

LatchEdgeEarliesttimesignalcanarriveatdestinationregisterandnotinterferewithdatasampledonpreviousclockedge第16页，共222页。SlackSetupSlack=SetupRequiredTime–DataArrivalTimeHoldSlack=DataArrivalTime–HoldRequiredTimeSlackmustbepositivetoensureproperoperationEquationsworkforinternalandI/Opaths第17页，共222页。Whyisthisimportant?QuartusreportstimingusingthisterminologyNoneedtomemorize!第18页，共222页。InputMaximumDelayMaximumDelayfromExternalDevicetoAlteraI/ORepresentsExternalDevicetco+PCBDelay-PCBClockSkewConstrainsRegisteredInputPath(tsu)AtcotsuAlteraDeviceExternalDevicePCBDelaytsuA≤tCLK–InputMaximumDelayInputMaximumDelaytsuACLKCLK第19页，共222页。InputMinimumDelayMinimumDelayfromExternalDevicetoAlteraI/ORepresentsExternalDevicetco+PCBDelay-PCBClockSkewConstrainsRegisteredInputPath(th)AtcothAlteraDeviceExternalDevicePCBDelaythA≤InputMinimumDelayInputMinimumDelaythACLKCLK第20页，共222页。OutputMaximumDelayMaximumDelayfromAlteraI/OtoExternalDeviceRepresentsExternalDevicetsu+PCBDelay-PCBClockSkewConstrainsRegisteredOutputPath(Max.tco)BtcotsuAlteraDeviceExternalDevicePCBDelaytcoB≤tCLK-OutputMaximumDelaytcoOutputMaximumDelayCLKCLK第21页，共222页。OutputMinimumDelayMinimumDelayfromAlteraI/OtoExternalDeviceRepresentsExternalDeviceth-PCBBoardDelayConstrainsRegisteredOutputPath(Min.tco)BtcothAlteraDeviceExternalDeviceBoardDelaytcoB≥OutputMinimumDelaytcoOutputMinimumDelayCLKCLK第22页，共222页。SDCTerminologyReviewTermDefinitionNodeBasictimingnetlistunit(ports,pins,registersorkeepers)KeeperPortsorregistersCellDevicebuildingblocks(e.g.look-uptables,registers,embeddedmultipliers,memoryblocks,I/Oelements,PLLs,etc.)PinInputoroutputsofcellsNetConnectionsbetweenpinsPortTop-levelinputsandoutputs(e.g.devicepins)第23页，共222页。SDCNetlistExampleSamplePinNames:ina|comboutinrega|dataininrega|clkinrega|regoutab|comboutab|datacinainbclkinregainregbabclk~clkctrloutregoutcomboutdatainclkdatacdatadinclk[0]regoutoutclkcomboutdatainSampleNetNames:ina~comboutabclk~clkctrlinregacell=atom/wysiwygpin=otermpin=itermport=I/Onetcell第24页，共222页。QuartusIISoftwareDesignSeries:TimingAnalysisTimingAnalysis&Settings第25页，共222页。Howdoestimingverificationwork?Everydevicepathindesignmustbeanalyzedwithrespecttotimingspecifications/requirementsCatchtiming-relatederrorsfasterandeasierthangate-levelsimulation&boardtestingDesignermustentertimingrequirements&exceptionsUsedtoguidefitterduringplacement&routingUsedtocompareagainstactualresults

INCLKOUTDQCLRPREDQCLRPREcombinationaldelays

CLR第26页，共222页。TimingAnalysisAgendaTimeQuestbasicsTiminganalysisbasicsTimingreportsTimingconstraintsExampleapplications第27页，共222页。TimeQuestTimingAnalyzerTimingengineinQuartusIIsoftwareProvidestiminganalysissolutionforalllevelsofexperienceFeaturesSynopsysDesignConstraints(SDC)supportStandardizedconstraintmethodologyEasy-to-useinterfaceConstraintentryStandardreportingScriptingemphasisPresentationfocusesonusingGUI28第28页，共222页。OpeningTimeQuestToolbarbuttonToolsmenuStand-alonemodequartus_stawCommandline29第29页，共222页。TimeQuestGUIReportPaneTasksPaneConsolePaneViewPaneMenuaccesstoallTimeQuestfeatures30第30页，共222页。TasksPaneProvidesquickaccesstocommonoperationsCommandexecutionReportgenerationExecutesmostcommandswithdefaultsettingsUsemenusfornon-defaultsettingsDouble-clicktoexecuteanycommand31第31页，共222页。ReportPaneDisplayslistofgeneratedreportscurrentlyavailableforviewingReportsgeneratedbyTaskspaneReportsgeneratedusingreportcommandsHighlightreporttoseedetailinViewwindow32第32页，共222页。TimingSummaryTableViewPaneMainviewingareathatdisplaysreporttablecontents&graphicalresultsTimingHistogramPath

SlackReport33第33页，共222页。ViewingMultipleReportsClick&drag‘+’signtodivideviewpaneintomultiplewindows34第34页，共222页。ViewingMultipleReportsExampleViewpanesplitintotwowindowsHighlightwindow,thenhighlightreportinReportspaneyouwouldliketoappearthereDragbarstoedgestoremovesplitsUseTargetPanebuttontoforceaselectedreporttoappearinapane35第35页，共222页。ConsolepaneAllowsdirectentryandexecutionofSDC&TclcommandsDisplaysequivalentofcommandexecutedbyGUIDisplaysTimeQuestoutputmessagesHistorytabrecordsallexecutedSDC&TclcommandsCopy&pastetocreatescriptsorSDCfiles36第36页，共222页。SDCFileEditor=QuartusIITextEditorUseQuartusIIeditortocreateand/oreditSDCSDCeditinguniquefeatures(for.sdcfiles)AccesstoGUIdialogboxesforconstraintentry(Edit

InsertConstraint)SyntaxcoloringTooltipsyntaxhelpTimeQuestFilemenu

New/OpenSDCFileQuartusIIFilemenuNewOtherFilestabPlacecursorovercommandtoseetooltip37第37页，共222页。SDCFileEditor(cont.)ConstructanSDCfileusingTimeQuestgraphicalconstraintcreationtools38第38页，共222页。BasicStepstoUsingTimeQuestGeneratetimingnetlistEnterSDCconstraintsCreateand/orreadinSDCfile(recommendedmethod)

orConstraindesigndirectlyinconsoleUpdatetimingnetlistGeneratetimingreportsSavetimingconstraints(optional)39第39页，共222页。1)GenerateTimingNetlistCreatestimingnetlist(pathdatabase)basedoncompilationresultsPost-synthesis(mapping)orpost-fitWorst-case(slow),best-case(fast)timingmodels,orsetoperatingconditions(neededforStratix®IIIandCyclone®IIIdevicesonly)Toexecute:NetlistmenuTaskspaneTclequivalentofcommandTcl:create_timing_netlist40第40页，共222页。2a)Createand/orReadinSDCFileCreateSDCfileusingSDCfileeditorReadinconstraints&exceptionsfromexistingSDCfileSkipifnoSDCfileExecutionReadSDCFile(TaskspaneorConstraintsmenu)Fileprecedence(ifnofilenamespecified)FilesspecificallyaddedtoQuartusIIproject<current_revision>.sdc(ifitexists)Tcl:read_sdc[<filename>]41第41页，共222页。2b)ConstrainDirectlyinConsoleAddnewconstraintsdirectlyNotautomaticallyaddedtoSDCfileUseGUIorConsolepaneNotneededifallconstraintsinSDCfileRecommendusingSDCfile(step2a)insteadtoeasemanagementandstorageofconstraintsExampleconstraints(describedindetaillater)create_clockcreate_generated_clockset_input_delayset_output_delay42第42页，共222页。UsingGUItoEnterConstraintsDirectlyMostcommonconstraintscanbeaccessedfromtheConstraintsmenuSameasEditmenuInsertConstraintsinSDCfileeditorUseifunfamiliarwithSDCsyntaxConstraintsmenu43第43页，共222页。ConstrainingUserMUSTenterconstraintsforallpathstofullyanalyzedesignTimeQuestonlyperformsslackanalysisonconstraineddesignpathsRecommendation:Constrainallpaths(clocks&I/O)NotasdifficultataskasitmaysoundWildcardsSingle,generalizedconstraintscovermanypaths,evenallpathsinanentireclockdomain44第44页，共222页。3)UpdateTimingNetlistApplySDCconstraints/exceptionstocurrenttimingnetlistGenerateswarningsUndefinedclocksPartiallydefinedI/OdelaysCombinatorialloopsUpdatetimingnetlistafteraddinganynewconstraintExecutionUpdateTimingNetlist(TaskspaneorNetlistmenu)Tcl:update_timing_netlist45第45页，共222页。4)GenerateTimingReportsVerifytimingrequirementsandlocateviolationsCheckforfullyconstraineddesignorignoredtimingconstraintsTwomethodsTaskspaneAutomaticallycreates/updatesnetlist&readsdefaultSDCfileifneededReportsmenuMusthavevalidnetlisttoaccessTaskspaneorReportsmenuDouble-clickonindividualreport46第46页，共222页。“OutofDate”ReportsAddingnewconstraintsinteractivelyinconsolecausescurrentreportstobe“outofdate”Updatetimingnetlist®eneratereports(reportright-clickmenu)NosuchwarningwhenusingSDCfile47第47页，共222页。ResetDesignCommandLocatedinTaskspaneFlushesalltimingconstraintsfromcurrenttimingnetlistFunctionalTclequivalent:delete_timing_netlistcommandfollowedbycreate_timing_netlistUses“Re-starting”timinganalysisonsametimingnetlistapplyingdifferentconstraintsorSDCfileStartinganalysisoverifresultsseemtobeunexpected48第48页，共222页。5)SaveTimingConstraints(Optional)write_sdccommandSavesallconstraints&exceptionsappliedtocurrentnetlistintoSDCfileUseifconstraintsaddedduringTimeQuestsessioninconsoleinsteadofSDCfileNotesSDCfilesgeneratedbyTimeQuestonlyifrequestedUse-expandoption(notinGUI)toconvertAltera-specificSDCcommandsintostandardSDCRunreport_sdccommand(console,Taskspane,orReportmenu)toseewhatwillgetwrittentoSDCfile49第49页，共222页。BasicStepstoUsingTimeQuest(Review)GeneratetimingnetlistEnterSDCconstraintsCreateand/orreadinSDCfile(recommendedmethod)

orConstraindesigndirectlyinconsoleUpdatetimingnetlistGeneratetimingreportsSavetimingconstraints(optional)50第50页，共222页。UsingTimeQuestinQuartusIIFlowEnableTimeQuestinQuartusIIprojectSynthesizeQuartusIIprojectUseTimeQuesttospecifytimingrequirementsVerifytiminginTimeQuestPerformfullcompilation(runFitter)51第51页，共222页。FollowTimeQuestflowUse-post_mapargumentforsynthesis(mapping)onlynetlistIfdesignalreadyfullycompiled,choose-post_fit(default)Taskslistcommanddefaultstopost-fit,somustuseNetlistmenuinGUIZeroICdelaysauto-enabledwithPost-mapAssumesnointerconnectdelaystodetermineifitwillbepossibletomeettimingTimingRequirements:CreatePost-MapNetlist52第52页，共222页。TimingRequirements:EnterConstraintsEnterconstraintsviaConstraintsmenuorConsolepaneConstraintsmenuavailableinmainTimeQuestwindowandinSDCFileEditor53第53页，共222页。UsingTimeQuestinQuartusIIFlowEnableTimeQuestinQuartusIIprojectSynthesizeQuartusIIprojectUseTimeQuesttospecifytimingrequirementsVerifytiminginTimeQuestPerformFullCompilation(runFitter)54第54页，共222页。EnablingTimeQuestinQuartusIITellsQuartusIItouseSDCconstraintsduringfittingFileorderprecedenceAnySDCfilesmanuallyaddedtoQuartusIIproject(inorder)<current_revision>.SDC55第55页，共222页。EnablingTimeQuestinQuartusIISoftwareNotes:Arria®GXonlysupportsTimequest.TimeQuestisenabledbydefaultfornewStratixIIIandCycloneIIIdesigns.56第56页，共222页。SDCconstraintsarenotstoredinQSFTimeQuestcanusescripttoconvertQSFtimingassignmentstoSDCConstraintsmenuDoneautomaticallyifnoSDCfileexistswhenfirstopeningTimeQuestSeeQuartusIIHandbookChapter,“SwitchingtotheTimeQuestTimingAnalyzer”fordetailsDifferencesbetweenClassicTimingAnalyzerandTimeQuestDetailsonconversionutilityOnlinetrainingalsoavailableSwitchingtotheTimeQuestTimingAnalyzerQuartusSettingsFile(QSF)57第57页，共222页。UsingTimeQuestinQuartusIIFlowEnableTimeQuestinQuartusIIprojectSynthesizeQuartusIIprojectUseTimeQuesttospecifytimingrequirementsVerifytiminginTimeQuestPerformfullcompilation(runFitter)58第58页，共222页。VerifyingTimingRequirementsViewTimeQuestsummaryinformationdirectlyinQuartusIICompilationReportOpenTimeQuestformorethoroughanalysisFollowTimeQuestflowRunTimeQuesteasy-to-usereportingcapabilities(Taskspane)ManydifferentreportingoptionsavailablePlaceTclreportingcommandsintoscriptfileEasyrepetition59第59页，共222页。TimeQuestSummaryReportsSDCfilesusedduringfittingClocksgeneratedTimingviolationsUnconstrainedpaths60第60页，共222页。3rd-PartyTimingAnalysisToolSupportSynopsysPrimeTimeMentorGraphicsTAU61第61页，共222页。TimingAnalysisAgendaTimeQuestbasicsTiminganalysisbasicsTimingreportsTimingconstraintsExampleapplications第62页，共222页。TimingAnalysisBasicsLaunchvs.latchedgesSetup&holdtimesData&clockarrivaltimeDatarequiredtimeSetup&holdslackanalysisI/OanalysisRecovery&removalTimingmodels第63页，共222页。Path&AnalysisTypesThreetypesofPaths:ClockPathsDataPathAsynchronousPaths*ClockPathsAsyncPathDataPathAsyncPathDQCLRPREDQCLRPRETwotypesofAnalysis:Synchronous –clock&datapathsAsynchronous* –clock&asyncpaths*Asynchronousreferstosignalsfeedingtheasynchronouscontrolportsoftheregisters第64页，共222页。Launch&LatchEdgesCLKLaunchEdgeLatchEdgeDataValidDATALaunchEdge: theedgewhich“launches”thedatafromsourceregisterLatchEdge: theedgewhich“latches”thedataatdestinationregister(withrespecttothelaunchedge,typically1cycle)第65页，共222页。Setup&HoldSetup: Theminimumtimedatasignalmustbestable BEFOREclockedgeHold: Theminimumtimedatasignalmustbestable AFTERclockedgeDQCLRPRECLKThValidDATATsuCLKDATATogether,thesetuptimeandholdtimeformaDataRequiredWindow,thetimearoundaclockedgeinwhichdatamustbestable.第66页，共222页。SetupSlack(cont’d)PositiveslackTimingrequirementmetNegativeslackTimingrequirementnotmetSetupSlack=DataRequiredTime –DataArrivalTime第67页，共222页。HoldSlack(cont’d)PositiveslackTimingrequirementmetNegativeslackTimingrequirementnotmetHoldSlack=DataArrivalTime –DataRequiredTime第68页，共222页。FPGA/CPLDorASSPASSPorFPGA/CPLDI/OAnalysisAnalyzingI/OperformanceinasynchronousdesignusesthesameslackequationsMustincludeexternaldevice&PCBtimingparametersreg1PREDQCLRreg2PREDQCLRCL*TdataTclk1Tclk2TCOTsu/ThOSCDataArrivalPathDataArrivalPathDataRequiredPath*Representsdelayduetocapacitiveloading第69页，共222页。Recovery&RemovalRecovery: Theminimumtimeanasynchronoussignalmust bestableBEFOREclockedgeRemoval: Theminimumtimeanasynchronoussignalmust bestableAFTERclockedgeDQCLRSETCLKTremValidASYNCTrecCLKASYNC第70页，共222页。Asynchronous=Synchronous?AsynchronouscontrolsignalsourceisassumedsynchronousSlackequationsstillapplydataarrivalpath=asynchronouscontrolpathTsu≈Trec;Th≈TremExternaldevice&boardtimingparametersmaybeneeded(Ex.1)ASSPreg1PREDQCLRFPGA/CPLDreg2PREDQCLROSCFPGA/CPLDreg1PREDQCLRreg2PREDQCLRExample1Example2DataarrivalpathDataarrivalpathDatarequiredpathDatarequiredpath第71页，共222页。WhyAreTheseCalculationsImportant?CalculationsareimportantwhentimingviolationsoccurNeedtobeabletounderstandcauseofviolationExamplecausesDatapathtoolongRequirementtooshort(incorrectanalysis)

Largeclockskewsignifyingagatedclock,etc.TimeQuestusesthemEquationstocalculateslackTerminology(launchandlatchedges,DataArrivalPath,DataRequiredPath,etc.)intimingreports第72页，共222页。TimingModelsQuartusIIsoftwaremodelsdevicetimingattwoPVTconditionsbydefaultSlowCornerModelIndicatesslowestpossibleperformanceforanysinglepathTimingat85ºCjunctiontemp.andVCCMINFastCornerModelIndicatesfastestpossibleperformanceforanysinglepathTimingat0ºCjunctiontemp.andVCCMAXWhytwocornertimingmodels?EnsuresetuptimingismetinslowmodelEnsureholdtimingismetinfastmodelEssentialforsourcesynchronousinterfacesThirdmodel(slow,0ºC)availableonlyforStratixIIIandCycloneIIIdevicestosupport65nmandsmallertechnology(temperatureinversionphenomenon)第73页，共222页。GeneratingFast/SlowNetlistSpecifythetimingmodeltobeusedwhencreatingyournetlistDefaultistheslowtimingnetlistTospecifyfasttimingnetlistUse-fast_modeloptionwithcreate_timing_netlistCommandChooseFastcornerinGUIwhen executingCreateTimingNetlist

fromNetlistmenuCANNOTrunfromTasksPane第74页，共222页。SpecifyingOperatingConditionsPerformtiminganalysisfordifferentdelaymodelswithoutrecreatingtheexistingtimingnetlistTakesprecedenceoveralreadygeneratednetlistRequiredforselectingslow,0ºCmodelforStratixIII&CycloneIIIUseget_available_operating_conditionstoseeavailableconditionsfortargetdevice第75页，共222页。TimingAnalysisAgendaTimeQuestbasicsTiminganalysisbasicsTimingreportsTimingconstraintsExampleapplications第76页，共222页。TimingReportsTimingresultsavailableinboththeQuartusIICompilationReportandTimeQuestTimeQuestincludesmoreextensivereportingcapabilitiesCreatereportswhilecreatingconstraints(post-mapnetlist)beforefittingtoseeifdesigncanmeettimingrequirementsCreatereportsafterfitting(post-fitnetlist)toverifythatplaced&routeddesignmeetstimingrequirements第77页，共222页。ReportinginTimeQuestMuchmorecontrolovergenerationofmanydifferenttypesofreportsSimplereportcreationbydouble-clickingcommonreporttypesintheTaskspaneorselectingfromReportsmenuComplexreportcreationwithcustomreportsorcommandlinereportingfeaturesUseTclscriptswithreportingcommandstoquicklyregeneratereportsforanalysis第78页，共222页。ReportDestinationsTargetedviewingpaneintheGUIDefaultdestinationforallreports-panel_name<name>:customizereportpanelnameConsoleReportresultsdisplayedintheconsole-stdout:enableconsolereportingOutputfileStorereportresultsinatextfile-file<name>:namefiletostoreresults-append:appendresultstoexistingfilespecifiedby-file第79页，共222页。ReportOutput(GUI)CustomreportsenttoGUIreportpanel第80页，共222页。CustomReportOutput(File)Customreport(ASCII)senttofile第81页，共222页。UtilityReportsReportSDCListsconstraintssuccessfullyappliedtothenetlist,organizedbyconstrainttypeCommand:report_sdcReportClocksListalltheclocksdefinedbyconstraintsinthedesignCommand:report_clocksReportIgnoredConstraintsListscommandsignoredbyTimeQuest,usuallyduetotyposorincorrectconstraintargumentsCommand:report_sdc-ignoredReportUnconstrainedPathsListsinputandoutputportsandpathsthathavenotbeenconstrainedCommand:report_ucpSeeexampleslaterwithactualconstraints第82页，共222页。OtherBasicTimingReportsReportClockTransfersSummarizesnumberofpathsthatcrossbetweenclockdomainsCommand:report_clock_transfersReportDatasheetSummarizestimingrequirementsfortheentiredesignTsu,Th,Tco,Tco(min),Tpd,Tpd(min)Command:report_datasheetCheckTimingChecksforpotentialtimingproblemswithdesignorconstraints-include<check_list>:performcheckonlyonlistedchecksCommand:check_timingReportFmaxSummaryReportpotentialFmaxforallclocksinthedesignCommand:report_clock_fmax_summary第83页，共222页。ReportingMacrosBuilt-inshortcuttasksthatgeneratemultiplereportsReportAllSummariesQuickcommandtogenerateallsummaryreportsReportTopFailingPathsReportAllI/OTimingsReportAllCoreTimingsReportsworstcaseslackonworstregister-to-registerpairsthroughoutdesignCreateAllClockHistograms(describednext)第84页，共222页。DetailedSlack/PathAnalysisCreatemorespecific/detailedreportsEx.DetailsonaspecificclockdomainEx.ViewtimingpathsbetweenparticularI/O®istersCreateusingTclcommandsorGUIUseGUItoseereportimmediatelyUseTclfileforrepeatabilityRecommendation:DonotplacereportingcommandsinSDCfile第85页，共222页。AdvancedReporting:ReportTimingreport_timing -from<source_nodes> -from_clock<source_clock_names> -rise_from_clock<source_clock_names> -fall_from_clock<source_clock_names> -through<thru_node> -to<destination_nodes> -to_clock<destination_clock_names> -rise_to_clock<destination_clock_names> -fall_to_clock<destination_clock_names> -less_than_slack<slack_limit> -npaths<#_of_paths_to_display> -setup|-hold|-recovery|-removal -detail<summary|path_only| path_and_clock|full_path> -file<file_name> -append -panel_name<report_name>第86页，共222页。report_timingArguments-setup|hold|removal|recoveryaremutuallyexclusiveDefaultis-setup-detailsummarygeneratesacondensedpathreportDetailedpathreports(path_only)isthedefault-npaths:numberofpathstoreport;defaultsto1第87页，共222页。ReportTiming(GUI)ChooseReportTiming(Reportsmenu)ordouble-clickonReportTiming(Taskspane)SelectwheretosendoutputreportTcl:report_timingSelectlevelofdetail第88页，共222页。SummarySlack/PathReportreport_timing-from_clockc100-to_clockc200\ -setup-npaths10-detailsummary\ -panel_name“Setup(c100toc200)Summary"CalculatedSlackSource&DestinationNodesSource&DestinationClocks第89页，共222页。OtherReportsReportTCCSChannel-to-channelskewmarginforLVDStransmittersReportRSKMReceiverskewmarginsforLVDSreceiversReportDDRCustomreportingforusewiththeALTMEMPHYmemorycontrollermegafunctionReportMinimumPulseWidthReportsminimumwidthsofclockpulsesrequiredtorecognizeclocktransitionsReportNetTimingandReportPathMoredetailedinformationaboutspecificnetsorpathsSeeHandbookandon-linehelpfordetails第90页，共222页。TimingAnalysisAgendaTimeQuestbasicsTiminganalysisbasicsTimingreportsTimingconstraintsExampleapplications第91页，共222页。ImportanceofConstrainingTiminganalysistellshowacircuitWILLbehaveProvidingtimingconstraintstellstoolshowyouWANTthedesigntobehaveConstraintspaintpictureofhowdesignshouldoperateBasedondesignspecs&specsfromotherdevicesonPCBProvidegoalsforfittertotargetduringcompilationProvidevaluestowhichtocomparetimingresultsTimeQuestperformslimitedanalysiswithouttimingconstraints第92页，共222页。TimingRequirements:EnterConstraintsAllconstraintsdiscussedcanbeeasilyaccessedinTimeQuestGUIConstraintsmenuofTimeQuestEditInsertConstraintmenuofSDCFileEditor第93页，共222页。SDCNetlistTerminologyTermDefinitionCellDevicebuildingblocks(e.g.look-uptables,registers,embeddedmultipliers,memoryblocks,I/Oelements,PLLs,etc.)PinInputoroutputsofcellsNetConnectionsbetweenpinsPortTop-levelinputsandoutputs(e.g.devicepins)第94页，共222页。SDCNetlistExampleSamplePinNames:ina|comboutinrega|dataininrega|clkinrega|regoutab|comboutab|datacinainbclkinregainregbabclk~clkctrloutregoutcomboutdatainclkdatacdatadinclk[0]regoutoutclkcomboutdatainSampleNetNames:ina~comboutabclk~clkctrlinregacell=atom/wysiwygpin=otermpin=itermport=I/Onetcell第95页，共222页。CollectionsSearchesandreturnsfromthedesignnetlistwithalistofnamesmeetingcriteriaUsedinSDCcommandsSomecollectionssearchedautomaticallyduringcommandsusageandmaynotneedtobespecifiedExamplesget_portsget_pinsget_clocksall_clocksall_registersall_inputsall_outputsSee“TimeQuestTimingAnalyzer”chapteroftheQuartusIISoftwareHandbook(Volume3)foracompletelist&descriptionofeach第96页，共222页。SDCTimingConstraintsClocksI/OAsynchronouspathsLatchesFalsepathsMulticyclepathsAbsolutedelaysTimeGroups第97页，共222页。WhatareclocksinSDC?Defined,repeatingsignalcharacteristicsappliedtoapointanywhereinthedesignInternal:appliedtoaspecificnodebeingusedasaclockindesign(portorpin)“Virtual”:Norealsourcein,ordirectinteractionwithdesignExample:Clocksonexternaldevicesthatfeedorarefedby