存储芯片技术的未来 The Future of Memory Chip technology

1

“TheFutureofMemoryChiptechnology”

February7,2024

Dr.GurtejSSandhu

PrincipalFellowandVicePresident,TechnologyDevelopment

©2022MicronTechnology,Inc.Allrightsreserved.Information,products,and/orspecificationsaresubjecttochangewithoutnotice.Micron,theMicronlogo,andallotherMicrontrademarksarethe

propertyofMicronTechnology,Inc.Allothertrademarksarethepropertyoftheirrespectiveowners.

MemoryTechnologyRoadmap

MemoryCostScalingOverTime

LogCost/GB($)

NANDCost/GBDRAMCost/GB

uuuuHistoricalCostTrend

Historical~40%YoYReductions

Historical~30%YoYReductions

New

Memory

Technology

Today

MOORE’S

SLOWING

Physical,Electrical,andMaterialsLimitations

EquipmentCapabilityCostandComplexity

©2015MicronTechnology,Inc.

PersistentChallenge

Product/DevicePerformanceBandwidth

Speed

Common

TechnologyChallenge

ScalingCost

Materials/EquipmentCostPowerConsumption

Demandforfaster

technicalinnovation

Time

HARStress-FreeGapfillRCManagement

ContactResistanceNext-GenPatterning

HAREtch

Large-AreaGapfillCellUniformity

StressModeling

DRAMNAND

3

N.Chandrasekar,IEDM2020

WorldwideChipOutput

DeviceCountfrom“ALL”typesofChips

TransistorCountMemoryvsNon-Memory

100%

Non-Memory

90%

80%

70%

60%

50%

40%

30%

Memory

20%

10%

0%

201020152019

February13,2024

4

Peekintothefuture

©2015MicronTechnology,Inc.Allrightsreserved.Information,products,and/orspecificationsaresubjecttochangewithoutnotice.All

informationisprovidedonan“ASIS”basiswithoutwarrantiesofanykind.Statementsregardingproducts,includingregardingtheirfeatures,

availability,functionality,orcompatibility,areprovidedforinformationalpurposesonlyanddonotmodifythewarranty,ifany,applicabletoanyproduct.Drawingsmaynotbetoscale.Micron,theMicronlogo,andallotherMicrontrademarksarethepropertyofMicronTechnology,Inc.Allothertrademarksarethepropertyoftheirrespectiveowners.

TheData-CentricEraisHere

BigDataAutomotiveMobileMedical

Day-to-dayroutinesdriveincreasedneedfordataandstorage

6

VS.

2010

1GB16GB

memorystorage

2020

16GB1TB

memorystorage

Usersspend6hourseachdayonmobile*

2.5quintillionbytesof

datacreateddaily

Thefirst

exascalesupercomputers

areduein2021**

**exaFLOPS—aquintillion(billionbillion)floating-pointoperationspersecond(1018FLOPS).

Leading-edge

AImodelcomplexity

isoutpacingMoore’sLaw

by8x*

*

/blog/ai-and-compute

MemorySolutionsforArtificialIntelligence(AI)

AIsolutionsrequiremorebandwidthandbetterperformance,utilizinglesspower

Powervs.Bandwidth

Energyvs.Bandwidth

CPUPerformanceDrivenbyTransistorScaling

Endof

Moore’s

Am-

dahl’s

Law

⇒

2X/

6yrs(12%/yr)

Law

⇒

Endof

Dennard

Scaling

2X/

20yrs(3%/yr)

⇒

Multicore

RISC2X/1.5

yrs(52%/yr)

CISC

2X/3.5yrs

(22%/yr)

2X/3.5

yrs

(23%/yr)

BasedonSPECintCPU.Source:JohnHennessyandDavidPatterson,ComputerArchitecture:AQuantitativeApproach,6/e.2018

CPUPerformanceDrivenbyTransistorScaling

6yrs(12%/yr)

TraditionalMoore’sLawisending.

It’stimefor“more”thanMoore.

DomainSpecificArchitecturesaretoday’sprocessor.

⇒

Multicore2X/3.5

yrs

(23%/yr)

Needtorearchitectsystems,software,andalgorithmsforDomainSpecificArchitectures(DSA).

CISC

2X/3.5yrs

(22%/yr)

RISC2X/1.5

yrs(52%/yr)

BasedonSPECintCPU.Source:JohnHennessyandDavidPatterson,ComputerArchitecture:AQuantitativeApproach,6/e.2018

DSAshavechangedtraditionaldesignprinciples

Significantincreaseinparallelism

Reducedoverhead

Rewriteofexistingalgorithmsandsoftwaretoreapadvantages

GoogleTPUv4

Optimizeddataflowstoreducestoragerequirements

Significantlyhigherbandwidthmemory,whennecessary

DeepLearningAccelerator

Domain-specificarchitectures(DSAs)optimizecomputeanddataflow,with

increasedrelianceonmemoryanddatamovement.

InspiredbyBillDally’s“TheFutureofComputing:Domain-SpecificAccelerators”

Bandwidth

Analog

Accelerator

~100GB

forof

Analogacceleratorspavethewayordersmagnitude

ofefficiencyimprovementsforcertaindomains.

In-/near-memoryandanalogcomputingenablePB/sbandwidthinareasonablepowerenvelope

100TB/s

IMC/

NMC

8GB

10TB/s

In/near-memorycomputesignificantlyincreases

efficiency,butrequiresmorethoughtfulsystemdesigns

Computationalstorageincreasesefficiencyatimprovedformfactors,especiallyforstaticdata.

1TB/s

HBM

8GB

ComputationalStorage

100GB/s

NAND

SSD1-16TB

DRAM

DIMM~100GB

10GB/s

DRAM

1GB

1GB/s

DSAscalingthroughincreasedmemoryefficiency

BubbleSize:Log(capacity)

NAND

Die

100GB

.

01pJ/b1pJ/b10pJ/b100pJ/b1nJ/b10nJ/b

Energy

Buildingblocksinamemory-centricworld

Goal:Explorearchitectures,frameworks,andoperatingsystemsforfuturememoryandstoragebuildingblocks

StorageControllers

MemoryControllers

NAND

SmartNAND

EmergingMemories

HBM

Accelerators

DDRDRAM

FPGAs

Extremememorybandwidth:>100TB/s

Memory

Logic

Logic

Logic

Logic

Logic

C

X

L

Limiteddeep,in-memorycomputecapability

A

n

alog

Arr

a

ys

Architecture-specificanalogbuildingblocks

Pivotalchallengestoaddress:

•Architectures/algorithmsfor100xhigherbandwidth

•Data-movement-firstlanguagesandframeworks

•Toolstomakememory-centricprogrammingeasier

•Frameworkswhichdeterminethebestmemory-centricexecutiontarget

•Efficienthandoffmechanismsforcompute-heavyoperations

Co-locatedmemory,storage,andaccelerators

H.SydneyTsai,AnalogMemory-basedTechniquesforAcceleratingDeepNeuralNetworks,StorageDeveloperConference(SDC),Sept22-23,2020

Available:

/watch?v=fERwXXdwSM0

14

AlternateStorageMechanismsResearch

MovingAtoms

-PCM,CBRAM,RRAM(Filament,MetalOxide),FeRAM,CNT,Molecular....

MovingSpins

-MRAM,STTRAM,Racetrack...

10-20yearsofactiveresearchbyIndustry

15February13,2024

ComparisonofMemoryCharacteristics

DRAM

STTRAM

PCM/1T1R

RRAM

Crosspoint

RRAM

NAND

ReadLatency

20ns

~50ns

~100ns-200ns

~100ns-200ns

~10us

WriteLatency

20ns

~50ns

~1us

~1us

~10us

ReadEndurance

>1e15

>1011

>107

>107

>107

WriteEndurance

>1e15

>1011

>106

>106

2K-100K

Write/Read

Energy/bit

<10pJ/bit

~25pJ/bit

~75pJ/bit

~75pJ/bit

>100pJ/bit

Alterability

~2KB

<2KB

~10,sB

~10,sB

LargeBlocks

Retention@RT

~milliseconds

Months

~Years

~Years

Years

ArealDensity

1x

~30x

17

ChallengesofMemoryScaling

DRAMistheonlymemorythatcanprovideabalanceofperformance,density,andenergyacceptabletobeclosetotheSOC.Noneofthe“10yrhorizon”EMschallengeit.

-DRAMscalingisnowbecomingchallengedduetoROIENDURANCE

-Wearenearthe“3Dinflection”forDRAM,exactpathisindebate,optionshighlyproprietary

NANDistheonlysolid-statememorythatcandeliverlowcostperbitatacceptableenergyandperformance.Noneofthe“10yrhorizon”EMschallengeit.

-3DNANDscalingwillbecomechallengedduetoROI

-Furtherb/cincreaseandperformance/costtradeoffslikelyCOST/Bit

-Beyond3Datopicofresearch

EmergingMemoryis(Kindof)emergingandisnowjudgedtolikelynotbesuitableforDRAM/NANDreplacementbutinsteadfortheiraugmentationinthememoryhierarchy

gdcron·

Outlook:DiscoveryofNewMaterialswithNovelMechanismsandPhysics

MaterialsattheNanoscale

(ReachingAtomicDimensions)

PhysicalProperties

(StrongQuantumEffectsorPurelyQM)

DevicePhysicswithNewStateVariables

(PredominantlyNon-equilibrium)

MemoryCell,AccessDevice,Interconnects

(DeviceApplications)

IntegratedCircuits;NewCompute,Memory,

andStorageSolutions

Needisforunearthingnovelmechanisms/physicsinnewmaterialsthatrevolutionizessemiconductorapplications,incontrasttotheoldapproachofscreeningtheperiodictabletofindmaterialsystemsforexistingdeviceconcepts

18

HeterogenousIntegration

©2018MicronTechnology,Inc.Allrightsreserved.Information,products,and/orspecificationsaresubjecttochangewithoutnotice.Allinformationisprovidedonan“ASIS”basiswithoutwarrantiesofanykind.

Statementsregardingproducts,includingregardingtheirfeatures,availability,functionality,or

compatibility,areprovidedforinformationalpurposesonlyanddonotmodifythewarranty,ifany,

applicabletoanyproduct.Drawingsmaynotbetoscale.Micron,theMicronlogo,andallotherMicrontrademarksarethepropertyofMicronTechnology,Inc.Allothertrademarksarethepropertyoftheirrespectiveowners.

PackagingLeadership

DevelopingaroadmaptoenablebandwidthandpowerleadershipforAIandHigh-PerformanceCMOSworkloads

HighBandwidth

Memory

ChiponSubstrateChipon/toWaferWafertoWafer

VolumeProductionYieldEnablementPathfinding

HeterogenousPackaging

20

Disruption

WaferBonding

Waferto

MemoryConstructionUsing

21

山Logic

-1-

lll

ml

HigherAccuracyAlignment

Source:IMECpresentationIEDM2020

MemoryArray-

DenseInterconnectionsbetweenMemoryArrayandCMOSRequireHighAccuracyBonding

gdcron·

•MemoryInterconnectionsbetweenCMOSandMemoryArraysrequire

•HighAccuracyBonding

•FinePitchConnectionswhichareenabledbyWafertoWaferBonding

•Co-developmentofLogicandMemoryandinterconnectlayouts,designandintegration.

•WafertoWaferBondingwith50nmAlignmentenablingsub1umhighdensity

interconnectionsneededinMemorytoadvancescaling.

•ImprovedMemoryPerformancewithEfficientFootprintenabledbyCMOSstackedwithArray

•MarkethasMemoryProductusingthistechnologyandadvancingonroadmap.

MicronMemorywith

Wafer-to-WaferBonding

Memory

Die

Co-Integrationof(3D)memory

andcomputeC2W

MemoryWaferConstruction

22

ChiptoWaferHybridBondingFacetoFaceConstruction

Phase1:

Phase2:

FinePitch(<10um)through-Siliconvia(TSV)

HighAccuracyBonding(<200nmAlign)

ChiptoWaferandFacetoBackConstruction•TSVRevealandBacksideMetals

Phase3:

WafertoWaferwithfullco-design

MemoryStack

Si

Thermal

Die

ComputeWaferConstruction

HybridBond

Si

Thermal

Die

FinePitch

Interconnect

+

=

LogicDie

SiDie

MemoryDie

MemoryStackLogicDie

Substrate

LogicDie

LogicDie

23

W2WAlignment<50nm

BondOverlayRoadmap–ExpectedversusDesired

ProblemStatement

•NoknownW2Wequipmentcapableof<50nmbondalignment

•Bondercapable50nmminimumwithbarewafersnofilm/nopattern/nostructure

•Incomingwaferdistortion(shape,inplane

distortion(IPD),residualstress)andvariabilityimpactalignmentaccuracy

•Estimateevery10nmflat-mapvariation=1nmregloss

Controlofwafershapeandplanarityacrossvariouslengthscales(e.g.,<5nm/100microns)

gsicron·

24

GuidingPrinciplesforTechnologyDevelopment

Security

Packaging

Metrology

Identifybreakthroughchallenges

Drivefullstackinnovation

Demonstrateprototypelevelsolutions

Mission:Bridgingthevalleyofdeath(betweenResearchandPilotmanufacturing)

gsicron·

25

MemorySystemCollaborationOverview

Developcapabilitiesformemorytoaddressfuturechallenges

Memory-centric

ComputeArchitectures

GrandGoal:

Focalpointformemory-centricand

materialdrivencollab.andprototyping

Enablesfull-stackcapabilitytoprototype

memory-centricdesignsandnoveldevices

Initialdemonstratorswillcomprise:

-Anapplication/infrastructure

MemoryStack

Si

Thermal

Die

-Amemory-centricarchitecture

Si

Thermal

Die

-Amemory/logicbondingprototype

-A3Dmemorystructure

FinePitchInterconnect

LogicDie

Memory-logicIntegration

NewMaterialsEmergingMemories

NanoscaleMaterials

PhysicalProperties

DevicePhysicswithNewStateVariables

MemoryCell,AccessDevice,Interconnects

IntegratedCircuits;NewCompute,Memory,

andStorageSolutions

Co-design,profile,establishvalueprop

Data-centerscale

Applicationto

Architecture

Profiling

26

FocusAreastoenableSystemLevelSolutions

IntegratedDesignFrameworkforMemoryCentricCompute

-TransformtheEDAeco-systemfromdigitalSoCfocustoco-designofmemory&computewithSW

Enablearchitectureexplorationacrossthefull-stackwithmulti-level,hierarchicalmodelingtoovercomesub-optimaldesignsfromlocalanalysisindiscretedomains

Integratedsystemlevelsimulationcapabilitiesspanninglogic,memoryandSWforanewclassofapplications

Automatedsystemverificationforself-tuning,self-adapting,&self-healingdesignsforresilientoperationforcompleteproductlife

Grounds-upsecuritydesignandscalableEDAinfrastructureformassivelyparallelorchestrationwithAIoptimizationofrun-time

Co-optimizednearandin-memorycomputearchitectures

-Addressingfundamentallimitationsoftheexistingcomputeparadigm

TheVonNeumanncomputeparadigmisfacingfundamentalchallengesinperformanceandenergyefficiencyduetodatamovementleadingtothedevelopmentofdata-centriccomputearchitecturesbasedonnearandin-memorycompute.

Bringtogethercomputeandmemoryexpertisetoprovideunprecedentedperformanceandenergyefficiency

-Memorycollaborationwithlogicandheterogeneousintegrationprograms

-Leveragethrough-silicon-via,chiptowaferandwafertowaferbondingcapability

End-to-endmemorysoftwareandhardwareco-design

-Establishmemorysystemsandsoftwaretestbed

Enablingnewmemories,memory-centricarchitecturesandmemory/computeintegrationrequiresadetailedunderstandingofmemoryworkloadsandoptimizationofthesoftwarestack

Partnerwithindustrycollaboratorstodriveadeeperunderstandingofmemoryusagemodels

-Memoryandstoragetiering

-Pooledmemoryandstorage

-Heterogeneouscomputeleveragingmemory-centricaccelerators

Cost

Memory

SoftwareSecurityCompute

memory

memory

memory

memory

memory

memory

memory

memory

memory

memory

4-highnear-memorycompute

storage

CPU

storage

storage

C