Introduction to Flash memory.ppt

1、Introduction to Flash memory,Ivan Chen,Topics,Flash memory overview Nor flash and uboot driver Nand flash and uboot driver SPI flash and uboot driver Multi-media card(MMC) Secure digital cards (SD),Flash memory overview,Flash memory is a non-volatile computer storage chip that can be electrically er

2、ased and reprogrammed. Its primarily used in memory cards, USB flash drivers, MP3 players and solid-state drives for general storage and transfer of data between computers and other digital products.,Flash memory overview (History),Flash memory (both NOR and NAND) was invented by Dr. Fujio Masuoka w

3、hile working for Toshiba 1980. Intel introduced the first commercial NOR type flash chip in 1988. NOR-based flash has long erase and write times, but provides full address and data buses. Toshiba announced NAND flash at the 1987. It has reduced erase and write times, and requires less chip area and

4、cell, thus allowing greater storage desity and lower cost per bit than NOR flash, however the I/O interface of NAND flash does not provide a random access external address bus.,Flash memory principle,Flash memory principle,The information is stored in Flash memory as an array of floating gate transi

5、stors, called “cells”, each of which stores one bit of information traditionally, Newer flash memory devices , referred to as multi-level cell devices, can store more than 1 bit per cell by varying the number of electrons placed on the floating gate of a cell. Flash memory cell functions by storing

6、charge in the floating gate, the presence of charge will then determine whether the channel will conduct or not. During the read cycle a “1” at the output corresponding to the channel being in its low resistance or ON state. The control gate is used to charge up the gate capacitance during the write

7、 cycle.,Flash memory overview (features),Arranged into blocks Each bit in a clean flash chip will be set to a logical one, and can be set to zero by a write operation. Resetting bits from zero to one cannot be done individually, but only by resetting a complete block. Memory wear: has a finite numbe

8、r of program-erase cycles. (should update out of place instead of in place),NOR vs NAND,NOR vs NAND,Onenand flash,Developed by Samsung Contain ram inside to emulate NOR interface, which combine the advantages of NOR and NAND Contain bad block management unit inside Read: send a read cmd and directly

9、 read internal ram. Write: directly write data to internal ram and send a write cmd. Read speed: 108MBps, nand(17MBps) Write speed: 9.3MBps, nand(6.8MBps), NOR (0.14MBps),Onenand flash,Serial flash,Serial flash is a small, low-power flash memory that uses a serial interface, typically SPI, for seque

10、ntial data access. Require fewer wires on the PCB than parallel flash memories, since it transmits and receives data one bit at a time.,SPI flash,Flash memory overview (Standardization),A group called the Open NAND Flash Interface Working Group (ONFI) has developed a standardized low-level interface

11、 for NAND flash chips. (Hynix , Intel, Micron Technology and Numonyx) Intel introduced a Common FLASH Interface (CFI) for NOR flash,Memory Technology Device,Memory technology devices (MTD) are a new type of device file in Linux for interacting with flash memory. The MTD subsystem was created to prov

12、ide an abstraction layer between the hardware-specific device drivers and higher-level applications. Although character and block device files already existed, their semantics dont map well to the way that flash memory devices operate.,Memory Technology Device,USB sticks , MMCs, SDs, Compact Flashes

13、 and other popular removable devices are not memory technology devices, but block devices. They contain flash chip inside , but they also contain Flash Translation Layer (FTL) above which emulates block device.,NOR flash (CFI),NOR flash (CFI),Common Flash interface (CFI) is a published, standardized

14、 data structure that may be read from a flash memory device. CFI allows system software to query the installed device to determine configurations, various electrical and timing parameters, and functions supported by the device. Basic Command Set (BCS) is a group of commands that have been used for y

15、ears on Intels and other vendors legacy products. These commands include Read Array, Read ID, Read Status Register, Clear Status Register, Program (Write), Block Erase, Erase Suspend, and Confirm/Resume.,NOR flash (CFI),Scalable Command Set (SCS) is the Extended Command Set that Intel uses to contro

16、l the functions of most CFI-enabled flash drivers. CFI allows the vendor to specify a command set that should be used with the component. These new commands include Set and Clear Lock Bits, CFI Query, Write to Buffer, Program Suspend, Status Configuration, and Full Chip Erase.,NOR Flash (memory Huer

17、istics Flowchart),CFI Query,NOR Flash (Possible array configurations),Single chip operating in x16 mode(16-bit data bus), chips may be capable of 8-bit accesses, but are operating only with 16-bit bus accesses Two chips each capable of 8- and 16-bit data bus accesses, but each only operating in a x8

18、 mode(8-bit data bus on each chip with a total array bus width of 16-bits) Two chips each only capable of 8-bit data bus accesses operating only in x8 mode(8-bit data bus per chip with a total array bus width of 16 bits),Jedec Query (old driver),Block Erase,Single byte program,Uboot nor flash driver

19、,CFI flash driver : for flash chip which is CFI compliant (drivers/mtd/cfi.flash.c) Jedec flash driver: for legacy flash chip which is not CFI compliant, need to provide low level operation chip by chip, load some chip parameters from software table.,Uboot nor flash driver,/*- * FLASH Info: contains

20、 chip specific data, per FLASH bank */ typedef struct ulongsize;/* total bank size in bytes*/ ushortsector_count;/* number of erase units*/ ulongflash_id;/* combined device ,Uboot nor flash driver (export interface),flash_init() flash_write() flash_erase() flash_protect(),NAND flash architecture(mic

21、ron 2G-bit nand flash),Nand flash architecture,Nand flash devices use a highly multiplexed 8/16-bit busI/O to transfer data, addresses, and instructions. 16-bit mode, commands and addresses use only the lower 8 bits, upper 8 bits are only used during data-transfer cycles. Five command pins(CLE, ALE,

22、 CE#, RE#, WE#) implement the NAND flash command bus interface protocol. Additional pins control hardware write protection(WP#), monitor the device ready/busy(R/B#) state, and enable block lock functionality(LOCK).,Nand flash architecture,Nand Flash architecture,The above nand is a 2-Gbit Nand devic

23、e and organized as 2048 blocks, with 64 pages per block. Each page has 2112 bytes total, comprised of a 2048-byte data area and a 64-byte spare area, which is typically used for ECC, wear leveling information.,Nand Flash operation,Nand flash operation,Program: can only program bits to 0, and assume

24、that you started with a previously-erased block. When Program page command is received, the input register is internally reset to all 1s, letting the user input only data bytes that he wants to program with 0 bits. Random data input: Its useful when you want to jump around within a page, to access E

25、CC data.,Nand flash operation,Read: starts with a command(00h), followed by five address cycles, followed by the read confirm(30h). After the read transfer time of approximately 25us, the data is loaded into the register and ready for output. Nand device actually has two registers: a data register a

26、nd a cache register. The Page read cache mode command lets you pipeline the next sequential access from the array while outputting the previously-access data.,Nand flash operation,Program page cache mode : provides performance improvement over normal Program page operations. This double buffered tec

27、hnique lets the controller input data directly to the cache register and uses the data register as a holding register to supply the programming of the arrays. Copy back : provides the ability to move data from one page to another internally without leaving the NAND device.,Nand Flash operation,Nand

28、flash (ECC),Nand flash includes extra storage on each page, which can store the ECC code as well as other information like wear-leveling or logical-to-physical block-mapping. ECC can be performed in hardware or software. During a programming operation, the ECC unit calculates the error-correcting co

29、de, the ECC code for respective data area is then written to the respective spare area. When data is read out, the ECC code is also read, and the reverse operation is applied to check that the data is correct.,Open Nand Flash Interface (ONFI),It defines a standardized NAND flash device interface tha

30、t provides the means for a system to be designed that supports a range of NAND flash devices without direct design pre-association. Unfortunately Samsung (the largest flash memory manufacturer) not joined this group.,ONFI (memory organization),ONFI (memory organization),A device contains one or more

31、 targets, a target is controlled by one CE# signal. A target is organized into one or more logical units (LUNs). A logical unit (LUN) is the minimum unit that can independently execute commands and report status. Specifically, separate LUNs may operate on arbitrary command sequences in parallel. A l

32、ogical unit contains at least one page register and a Flash array. The number of page register is dependent on the number of interleaved operations supported for that LUN. A flash array contains a number of blocks. A block is the smallest erasable unit of data within the Flash array of a LUN. A page

33、 is the smallest addressable unit for read and program operations.,ONFI (addressing),Column address: used to access bytes or words within a page, i.e. the column address is the byte/word offset into the page. Row address: used to address pages, blocks and LUNs. When both column and row addresses are

34、 required to be issued, the column address is always issued first in one or more 8-bit address cycles. The row addresses follow in one or more 8-bit address cycles. Block erase doesnt require column address.,ONFI (interleaved addressing),ONFI (command set),Uboot nand flash driver,Uboot nand flash dr

35、iver,struct mtd_info,erase,read,write,read_oob,write_oob,nand chip implementation,nand_erase,nand_read,nand_write,nand_read_oob,nand_write_oob,sync,suspend,resume,block_isbad,block_markbad,nand_sync,nand_suspend,nand_resume,nand_block_isbad,nand_block_oob,Uboot nand flash driver,nand_init(),board_na

36、nd_init(),nand_scan(),add_mtd_device(),Chip related initialization,Fills out all function pointers and scan a bad block table,Uboot nand flash driver,struct nand_chip void _iomem*IO_ADDR_R; void _iomem*IO_ADDR_W; uint8_t(*read_byte)(struct mtd_info *mtd); u16(*read_word)(struct mtd_info *mtd); void(

37、*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); void(*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); int(*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); void(*select_chip)(struct mtd_info *mtd, int chip); int(*block_bad)(struct mtd_info *mtd, loff_t ofs, int

38、 getchip); int(*block_markbad)(struct mtd_info *mtd, loff_t ofs); void(*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); int(*dev_ready)(struct mtd_info *mtd); void(*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); int(*waitfunc)(struct mtd_info *mtd, struct n

39、and_chip *this); void(*erase_cmd)(struct mtd_info *mtd, int page); int(*scan_bbt)(struct mtd_info *mtd); int(*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); int(*write_page)(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int page, int cach

40、ed, int raw);,Read page with ecc,Read page buffer with size=eccsize Calculate a ecc Read out of band data Get original ecc_code according to eccpos from oob Correct the data buffer.,Write page with ecc,Write page data with size=eccsize Calculate the ecc Write the calculated ecc to oob.,Bad block man

41、agement,Most nand chips mark the bad blocks at a defined position in the spare area. (AG-AND chips is a exception) Those blocks must not be erased under any circumstances as the bad block information would be lost. It is possible to check the bad block mark each time when the blocks are accessed by

42、reading the spare area of the first page in the block, but it is time consuming so a bad block table is used.,Bad block table,Per device : the bad block table contains all bad block information of the device which can consist of multiple chips Per chip: A bad table is used per chip and contains the

43、bad block information for this particular chip. Fixed offset: The bad block table is located at a fixed offset in chip. Automatic placed: The bad block table is automatically placed and detected either at the end or at the beginning of a chip (device). Mirrored tables : the bad block table is mirror

44、ed on the chip to allow updates of the bad block table without data loss.,SPI flash and uboot driver(SPI bus),SPI: Serial Peripheral Interface Bus, which is a synchronous serial data link standard operates in full duplex mode. Devices communicate in master/slave mode where the master device initiate

45、s the data frame. Multiple slave devices are allowed with individual slave select(chip select). Sometimes SPI is called “four-wire” serial bus. SCLK: Serial Clock (output from master) MOSI, SIMO: Master output and slave input (output form master) MISO, SOMI: Master input, slave output (output from s

46、lave) SS : Slave select,SPI flash and uboot driver(SPI bus data transmission),SPI flash and uboot driver(SPI bus data transmission),To begin a communication, the master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports, commonly in th

47、e range of 1-70MHz. During each SPI clock cycle , a full duplex data transmission occurs: the master send a bit on the MOSI line, the slave read it from the same line; the slave sends a bit one the MISO line, the master read it from the same line. Transmissions normally involve two shift registers o

48、f some given word size . Data is usually shifted out with the most significant bit first, while shifting a new least significant bit into the same register. After that register has been shifted out, the master and slave have exchanged register values .,SPI flash (ATMEL),SPI flash (ATMEL),SPI Flash (

49、ATMEL)(Operations),Main memory page read Main memory page to buffer 1/2 transfer Main memory page to buffer 1/2 compare Buffer 1/2 to main memory page program with built-in erase Buffer 1/2 to main memory page program without built-in erase Page erase Block erase Main memory page program through buf

50、fer Auto page rewrite Buffer 1/2 read Buffer 1/2 write Status register read,SPI flash uboot driver,spi_flash_probe,spi_flash_read,spi_flash_write,spi_flash_erase,struct spi_flash,chip_read,chip_write,chip_erase,MMC,MMC is a flash memory card standard, unveiled in 1997 by Siemens AG and SanDisk, based on Toshibas NAND flash. Originally use 1-bit serial interface, newer versions allow transfers of 4 or 8 bits at a time.,MMC Block Diagram(Kingmax mmc),MMC,MMC interface: CMD, CLK, DAT CID : card identification re