集成电路课件.ppt

1、集成电路分析与设计,第 1 讲 认识集成电路设计及其设计过程,集成电路分析与设计课程主要介绍什么内容?,CMOS数字集成电路(CMOS digital IC) IC的发展历史及现状(History of IC) IC 设计流程和方法(Design process and Methodology) IC 制造工艺技术(Fabrication process) IC EDA（CAD）工具使用(EDA tools) CMOS反相器设计(CMOS Inverter) CMOS组合逻辑门设计(Combinational Logic Circuit) CMOS时序逻辑电路设计(Sequential Log

2、ic Circuit ) IC 版图设计(Layout) IC 仿真技术(Simulation) 存储器电路设计介绍(Memory Circuits) 模拟IC设计介绍(Analog IC),集成电路分析与设计课程信息,课程性质：是一门专业基础课程 主要介绍CMOS数字集成电路设计的基础知识 共40课时（32理论课时+8实验课时） 完成4个实验 对准备从事IC行业的学生来讲，本课程只是一个基础，还需要继续深入学习更多关于IC设计的知识，如数字IC深入，模拟IC，RF IC等。,实验内容（共8学时）,实验一（2学时） 反相器电路设计（ Simulation and Layout ） 实验二（2学

3、时） NAND电路设计（ Simulation and Layout ） 实验三（2学时） AND 电路设计（ Simulation and Layout ） 实验四（2学时） D触发器电路设计（ Simulation and Layout ）,Project（选作内容）,完成一个4 4 SRAM芯片的设计 3人一组 项目过程： A 期中Oral presentation B 期末Oral presentation C 项目报告书一份 D 3人项目成绩相同,Grading Policy,课堂提问和作业 10% 实验 20% 考试 （开卷） 70% 规则： （1）1个问题和4次作业，每次/个2分

4、，共10分； （2）每个实验完成得5分，共20分； （3）点名1次不到，10分没了； （4）抄作业，抄实验报告，相应分数没了； （5）请假规则：必须有正规请假手续和课前请假。,本课程推荐书目,教材 中文版 周润德等 译，数字集成电路设计透视第二版，电子工业出版社 (Jan M. Rabaey, et al. Digital Integrated Circuits, 2nd e, Prentice Hall, 2004) 参考书 Sung-Mo (Steve) Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis low

5、er power consuption; more reliable. Integration reduces manufacturing cost（降低成本） BOM (Board of Materials) cost reduces Mass IC production reduces cost,Electronics Industry,Design, fab, application Education Software Communication/Networking Fab cost: $2-$3 billion Driving force of world economy Larg

6、e investment: fab, packaging, design, EDA,Pentium 4 “Northwood” 55M transistors / 2-2.5GHz L=0.13m,Moores Law (1965),Gordon Moore Intel Founder “The number of transistors on a chip doubled every 18 to 24 months.”,Electronics, April 19, 1965.,Gordon Moore Intel Co-Founder and Chairmain Emeritus Image

7、 source: Intel Corporation ,Information Revolution,Electronic system in cars. Electronic financial system: e-banking,e-money, e-stock, RFID lable Personal computing/entertainment Medical electronic systems. Internet: routers, firewalls, servers, storages Electronic library (Google, .) DVD R/W, HDTV,

8、 Interactive TV In general, consumer electronics etc .,Challenges of IC Design,Complexity: Multi-million transistors on a single chip (smaller size/faster speed) Multiple and conflicting specifications for high performance (power/speed/throughput) Competition: Short design time Design Tools: Multipl

9、e tools involved, Complex design flow,Related to IC Jobs, Layout designers Circuit designers (Digital/Analog/RF) Architects Test/Verification engineers Fabrication engineers System designers (SoC) CAD tool programmers Embedded System developers Software programmers,The Transistor Revolution,First tr

10、ansistor Bell Labs, 1947,J. Bardeen, W. Shockley, and W. Brattain (1956 Nobel prize Laureate),1958年 J. Kilby（TI）研制成功第一个集成电路 1959年 R. Noyce（Fairchild）第一个利用平面工艺制成集成电路,The First Integrated Circuits,The First Integrated Circuits,Bipolar logic 1960s,ECL 3-input Gate Motorola 1966,First commercial IC logi

11、c gates Fairchild 1960 TTL 1962 into the 1990s ECL 1974 into the 1980s,Intel 4004 Micro-Processor,1970 2300 transistors 1 MHz operation,Intel Pentium (IV) microprocessor,Pentium 4 “Northwood” Commercial Production: Year 2001 L=0.13m 6ML Cu Low-k FC-PGA2,MOSFET Technology,MOSFET transistor - Lilienfe

12、ld (Canada) in 1925 and Heil (England) in 1935 CMOS 1960s, but plagued with manufacturing problems (used in watches due to their power limitations) PMOS in 1960s (calculators) NMOS in 1970s (4004, 8080) for speed CMOS in 1980s preferred MOSFET technology because of power benefits BiCMOS, Gallium-Ars

13、enide, Silicon-Germanium SOI, Copper-Low K, strained silicon, High-k gate oxide.,Worldwide Semiconductor Revenue,Source: ISSCC 2003 G. Moore “No exponential is forever, but forever can be delayed”,1 Wafer in 1964 vs. 300 mm (12 ”) Wafer in 2003,IBM Power PC 970 (130nm) 2003,1.8 Ghz 58 M 118 mm2,Appl

14、e Power G5, the fastest PC in 2003, has dual PPC 970 CPU,Two chips you are seeing today,Microprocessor,ASIC (Application Specific IC),State-of-the Art: Lead Microprocessors,State-of-the Art: Lead Microprocessors (up to date),Pentium 4 180 nm (2001) 1.7 G Hz 42 M transistors 217 mm2 Pentium 4 130 nm

15、(2003) 3.2G Hz 55 M Transistors 131 mm2 Pentium 4 90 nm (2004) 3.4 Hz 125 M Transistors 112 mm2 Pentium on 65nm (2005/2006) 250 Million Pentium on 45nm (2007) 400 to 500 Million,(All use 0.13 um technology except Pentium 4 Prescott, which uses 90 nm tech),State-of-the Art: Lead Microprocessors (up t

16、o date),300mm wafer and Pentium 4 IC. Photos courtesy of Intel.,What A Digital Designer Needs to Know .,“Microscopic Problems” Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution.,“Macroscopic Issues” Time-to-Market Millions of Ga

17、tes High-Level Abstractions Reuse & IP Availability systems on a chip (SoC) Predictability etc.,95%,如何设计一个集成电路？,The VLSI design process,工程的艺术,May be part of larger product design. Major levels of abstraction: specification architecture logic design circuit design layout design,Major Segments of IC I

18、ndustry,Fabless Design Houses,EDA Tools Companies,Design Service Companies,Library & IP Providers,Dedicated IC Manufacturers (Foundry),Post: EDA: Electronic Design Automation IP: silicon Intellectual Property IDM: Integrated Device Manufacturer,Integrated service,Packaging & Testing Houses,ASIC Desi

19、gn Styles,Full Custom Design Flow Circuit is created by composing a transistor netlist SPICE simulation is performed to verify the circuit Known as “capture-and-simulate” paradigm Layout is mostly done manually Popular for high-performance microprocessors & memories Cell-Based Synthesis Flow Design

20、is first described by Hardware Description Language (e.g., Verilog and VHDL) Based on a cell library, netlist is created by synthesis tools Known as “describe-and-synthesize” paradigm Layout can be done through automatic tools,Detailed Custom Design Flow,Block Specification (Finite State Machine, Ar

21、ithmetic Expression, Boolean Expression),Logic Design,Gate-Level Netlist,Transistor Netlist,Technology Mapping,SPICE Simulation,SPICE Model,Layout Design,Layout,Layout Rules,Design Rule Checking (DRC) Layout vs. Schematic Check (LVS),Parasitic (or wiring) RC extraction,Post-Layout SPICE Simulation,C

22、heck if SPEC is met ? If yes, done. Otherwise, go back to optimize the design,A Simple Example,Functionality One-bit binary full-adder Technology 1 mm n-well CMOS technology Speed Input to output delay 5 ns Area 3000 mm2 Power Dissipation 1 mW at 5 volts and 200 MHz,Full-adder,A,B,Sum,Carry_out,C,Lo

23、gic Design,Logic minimization trick: The carry_out signal is used to realize the function of signal sum in order to reduce the overall circuit size.,Todays logic synthesis tools (such as Design Compiler) incorporating some advanced algorithms, is able to perform automatic logic minimization.,x = Car

24、ry_out,Transistor-Level Schematic,Technology mapping Many simple AND OR gates are merged into a complex gate (or a cell in the cell library) Transistor aspect ratio pMOS (W/L) is usually larger than nMOS (W/L), e.g., 2:1,x,y,x,y,x = (AB+BC+CA) y = (A+B+C) x + ABC),Initial Layout,Post-layout SPICE si

25、mulation includes the “parasitic resistance & capacitance” is more accurate than the pre-layout simulation (pre-sim),Ratio of channel widths 2:1,I/O Simulation Waveforms,Propagation time tPHL or tPLH as defined above Low-to-high propagation time （传播延时） tPLH = 8.2 ns ! Got to go back to optimize the

26、design !,Optimized Layout,Transistor Sizing changes the aspect ratios (W/L) of selected transistors A larger aspect ratio may lead to a higher speed Wire Sizing is also more recently proposed,Propagation Delay 5 ns !,Full Custom Design Example（another),A/D,PLA,I/O,comp,RAM,Cell-Based Design Flow,Architecture design,System-level integration,layout,No violation,Memory module,Functional model,Testbench,RTL code,Cell