半导体制造流程与IC产业链简介[1].ppt

1、Introduction on Fab flow and semiconductor industry - for IT related employee,Morris L. Yeh UMC.Fab8AB.PEI.Logic2,Outline,1. Fab flow and Transistor working,2. IC manufacturing chain,3. Filed application,4. The Trend,The Roadmap,1.1 Transistor Working,1. Whats the Transistor ?,2. Whats the Transisto

2、r structure ?,3. Hows the transistor working ?,4. Transistor and System revolution,3.1 Hows the clock running in the transistor ring?,3.2 Hows the information broadcasting in a system ?,1. Whats the Transistor ?,Transistor Working,In Digital application, the transistor play the role of switch in the

3、 system just like a mechanical switch , it means that the key component to storage the 0 and 1,State 1,State 0,But we deployed the Solid-State and Quantum physics to realize the solid-state switch - Transistor in silicon industry, its more size shrinkage, high speed, high performance and lower energ

4、y required than the prior arts.,State 1,State 0,2. Whats the Transistor structure ?,Transistor Working,LDD,POLY,The transistor included 3 terminal which likes the switch : 1. Poly Gate play the role of control or input terminal, the Drain play the role of output terminal and the Source play the role

5、 of reference or ground.,3. Hows the transistor working ?,Transistor Working,Voltage on the Drain terminal (output),=,In the Digital application, the transistor behaviors more likes a Capacitor : 1. Drain Bias ( Capacitor Charge ) : The charge storage on the Drain side. 2. Gate Bias ( Capacitor Disc

6、harge ) : The storage charge flow from Drain to Source 3. Drain Bias again ( Gate floating, Capacitor Recharge ) : The charge storage again.,3.1 Hows the clock running in the transistor ring?,The video shown the 49 stages NOT gate series which constructed the ring oscillator, In the left NOT gate di

7、agram, if the input terminal become state 0, the PMOS was turn ON, and NMOS turned off, it means that the Vcc flow into Output terminal, the Output state become 1, and according quantum physics, the current flow the channel means that electron-hole pair recombination, and the light emission will be

8、detected by the cooled infrared camera. The Ring Oscillator was the tool to measure the system clock and speed.,3.2 Hows the information broadcasting in a system ?,Generally, theres a few people could understood the information broadcasting in a chip, especially on the system debug, the product engi

9、neer hard to detect the defect in system level. The liquid-nitrogen-cooled infrared Camera could detect the hot spot emission which generated by the electron-hole pair combination. The defect could be detected once the signal flow to the defect node, the system will be hold and hot spot frozen on th

10、e defect node.,FIG. 1. The first transistor. Brattain and Bardeens pnp point-contact germanium transistor operated as a speech amplifier with a power gain of 18 on December 23, 1947. (Bell Labs, Lucent),FIG. 3. The worldwide smallest transistor Gate length 0.061 um. (Bell Labs, Lucent),FIG. 2. The U

11、MC post generation 0.25um standard transistor ( UMC ),4.1 The Transistor revolution,The First Transistor 1947 Bell labs.,The UMC 0.25um Transistor 1999, UMC,The worldwide leadship 2001 Bell labs. Lucent,Device Integration and Technology drive,1.2 Fab flow,1. Lithography concept and cycle,4. Transist

12、or Layer (Front-end) definition,5. Routing Layer (Back-end) definition,3. Module composition and integration,2. Module definition,Lithography concept - physical cycle,ThinFilm-PHOTO-ETCH Physical layer formation cycle,Fab Flow,Lithography concept - Implant cycle,Diffusion-PHOTO- Diffusion Implant la

13、yer cycle,Fab Flow,1.2 Fab flow,1. Lithography concept and cycle,4. Transistor Layer (Front-end) definition,5. Routing Layer (Back-end) definition,3. Module composition and integration,2. Module definition,Photo: Raw material : Reticle, Photo Resist Equipment : I-Line(MUV), DUV, EUV (Stepper, SCANNE

14、R) Vendors: Nikon, ASML,2. Module definition - PHOTO,The PHOTO concept was general Optics lithography to reproduce the specific patterns. Today we deployed the UV Excimer laser for the light, According to Optics principle, generally the wavelength of the light should be less than one tenth of half p

15、itch, so if the technology shrink, the Exposure light source should be pushed into deeply UV zone.,Thin-Film: Raw material : Metal Target, Chemical Equipment : Sputter, RTP, CVD (AP, PE, LP, SP, MO), Scubber Vendors: AMAT, Novellus, TEL, ASM.,2. Module definition - Thin Film,In general we can split

16、the Thin-Film into two field, one is Physics dominated (PVD), the other is Chemical dominated (CVD) The PVD means that no chemical reaction assisted in the process, just simply accelerated Ar atom to bombard the target to evaporate the target and deposit on the wafer, such likes Sputter. The CVD mea

17、ns that the chemical reaction on the wafer or chamber to deposit a film on the surface,CVD,PVD,Chemical reaction,Etch Raw material : Solvent, Reactive gas Equipment : Dry Etch (RIE), Wet Bench (Chemical Station) Vendors: AMAT, Novellus, TEL, ASM.,2. Module definition - ETCH,In general we can call th

18、at RIE in the term of Dry etching, the dry etching which dominated by the Physical Ion bombard and chemical reaction with the surface to evaporated the byproducts.,Reactive ion bombard,Diffusion Raw material : Chemical Gas, Isotope gas Equipment : Implanter , Furnace Vendors: Eaton, Varian, KE, TEL.

19、,2. Module definition - Diffusion,In the diffusion, therere two methods to deliver the dopant into the silicon wafer : . Implant : To accelerate the isotope and direct bombard the wafer to deliver the dopant into right depth with right concentration. . Furnace : To use thermal diffusion potential to

20、 deliver the dopant into right depth with right concentration.,CM P Raw material : Slurry, polish pad Equipment : CMP (W-CMP, Oxide-CMP, Cu-CMP) Vendors: AMAT, COBAT, Strasbaugh,2. Module definition - CMP,In general, the CMP like the polish arts, but deployed the chemical-mechanical assistant. There

21、re two factors dominated the CMP process: . First is chemical hydrolysis slurry to hydrolyze the surface, .Second is the slurry abrasive to remove the hydrolyte which under the mechanical dominated.,1.2 Fab flow,1. Lithography concept and cycle,4. Transistor Layer (Front-end) definition,5. Routing L

22、ayer (Back-end) definition,3. Module integration,2. Module definition,Process Flow,Layer (Route),Module(Step),3. Module integration,1.2 Fab flow,1. Lithography concept and cycle,4. Transistor Layer (Front-end) definition,5. Routing Layer (Back-end) definition,3. Module composition and integration,2.

23、 Module definition,Brief Process Flow - First Layer (Diffusion),P-sub (Silicon wafer),SiN (Nitrid),Pad oxide,1.1. Wafer Start 1.2. PAD Oxidation 110A (stress buffer) 1.7. SiN (Nitrid) Deposition 1.5KA 1.8. Diffusion Lithography : 1.8.1 P.R. coating 1.8.2 Stepper Exposure 1.8.3 Development,Photo Resi

24、stor coating,Stepper Exposure,Brief Process Flow - First Layer (Diffusion) cont,1.7. Trench (STI) Plasma Etching 1.7.1 SiN Etching 1.7.2 Silicon Etching 1.8. Photo Resistor remove,Brief Process Flow - First Layer (Diffusion) cont,1.7. APCVD STI refill 1.7.1 Liner Oxide Growth 1.7.2 APCVD Oxide depos

25、ition 1.7.3 STI Furnace 1000C Densify 1.8. STI CMP 1.9. SiN remove,Brief Process Flow - Well formation,P.R. Coating,Stepper Exposure,2.1 N-WELL Formation : 2.1.1 N-WELL PR coating 2.1.2 N-WELL Lithography 2.1.3 Development 2.1.4 N-WELL implant 2.1.5 PR stripping 2.2 P-WELL Formation : 2.2.1 P-WELL P

26、R coating 2.2.2 P-WELL Lithography 2.2.3 Development 2.2.4 P-WELL implant 2.2.5 PR stripping,P.R. Coating,Stepper Exposure,N-WELL Implant 1. N-WELL- 1 2. N-WELL- 2 7. P MOS - VT 8. P MOS anti-punch,P-WELL Implant 1. P-WELL- 1 2. P-WELL- 2 7. N MOS - VT 8. N MOS anti-punch,Brief Process Flow - Gate O

27、xide and POLY,PR coating,Gate Oxide,Stepper Exposure,Gate Oxide 2,UPOLY growth,3 Gate Oxide Formation : 3.1 Thick Gate Oxide Growth 3.2 PR coating 3.3 TG Lithography 3.4 Development 3.5 RCA-A Wet etching 3.6 PR stripping 3.7 Thin Gate Oxide Growth 4. Poly Growth 4.1 undope. POLY growth 4.2 N+POLY PR

28、 coating 4.3 N+POLY Lithography 4.4 Development 4.5 N+POLY implant and PR Strip,PR Coating,N+POLY implant,Stepper Exposure,Brief Process Flow - Gate Engineering,PR coating,Stepper Exposure,N-LDD Implant,P-LDD implant,5 Poly Gate Formation : 5.1 Poly annealing 5.2 PR coating 5.3 POLY Lithography 5.4

29、Development 5.5 POLY Gate etching 5.6 PR stripping 5.7 Thin Oxide Growth 6. LDD (Light Dope Drain) implant 6.1 N-LDD Lithography (ellipsis) 6.2 NLDD / N-PKT implant 6.3 P-LDD Lithography (ellipsis) 6.4 PLDD / P-PKT implant,Brief Process Flow - Drain Engineering,P+ Implant,N+ implant,7 Poly Gate Form

30、ation : 7.1 Poly annealing 7.2 PR coating 7.3 POLY Lithography 7.4 Development 7.5 POLY Gate etching 7.6 PR stripping 7.7 Thin Oxide Growth 8. LDD (Light Dope Drain) implant 8.1 N-LDD Lithography (ellipsis) 8.2 NLDD / N-PKT implant 8.3 P-LDD Lithography (ellipsis) 8.4 PLDD / P-PKT implant,1.2 Fab fl

31、ow,1. Lithography concept and cycle,4. Transistor Layer (Front-end) definition,5. Routing Layer (Back-end) definition,3. Module composition and integration,2. Module definition,Brief Process Flow - ILD Passivation,9. Salicide Formation : 9.1 PETEOS-500A Cap Oxide dep. 9.2 SAB (Salicide-Block) Lithog

32、raphy (ellipsis) 9.3 Ti/Co sputtering 9.4 Salicidation RTP C49 annealing 9.5 Salicidation RTP C54 annealing 9.6 Ti residual Semi-tool wet clean 10. ILD Passivation 10.1 SiN 300A deposition (Moisture and sodium block) 10.2 AP-USG deposition (Gap filling and B,P trap) 10.3 TEOS-BPSG-14K deposition (re

33、-flow and planarization) 10.4 ILD CMP,PR Coating,Brief Process Flow - Contact Plug,Metal 1,DUV Stepper Exposure,11. Contact Plug Formation : 11.1 Contact Lithography 11.2 Contact Plasma Etching 11.3 PR strip 11.4 Barrier layer deposition (Ti + TiN for well contact) 11.5 RTP annealing 11.6 Glue Layer

34、 deposition (Ti + TiN for plug adhesion) 11.5 WCVD filling 11.6 WCMP 11.7 Metal Liner deposition (Ti + TiN for Metal adhesion) 11.8 Metal Sputter,Brief Process Flow - Backend routine (Aluminum line),Cap Oxide,PR Coating,Metal 2,Stepper Exposure,Stepper Exposure,12. IMD deposition 12.1 HDP-Oxide depo

35、sition ( Gap filling) 12.2 PE-Oxide Deposition ( Planarization and uniformity) 12.3 IMD CMP 12.4 Cap PE-Oxide 13. MVIA plug formation 13.1 MVIA Lithography cycle 13.2 MVIA Etching and PR strip 13.3 Glue Layer deposition (Ti + TiN for plug adhesion) 13.4 WCVD filling 13.5 WCMP 13.6 Metal Liner deposi

36、tion (Ti + TiN for Metal adhesion) 13.7 Metal Sputter,Brief Process Flow - Aluminum line,Brief Process Flow - Backend routine (Copper Dual Damascene),PR Coating,Stepper Exposure 2,Stepper Exposure 1,Stepper Exposure 3,14. ILD/M1 Damascene 14.1 PEOX-3.6K deposition 14.2 M1 Lithography 14.3 M1 Trench

37、Etching 14.4 M1 Cu Electroplate (ECP) 14.5 Cu CMP 15. M2/ MVIA1 Dual Damascene 15.1 PEOX-9K deposition 15.2 M2 Lithography 15.3 M2 Trench Etching 15.4 MVIA1 Lithography 15.5 MVIA1 Plug Etching 15.6 Trench Liner deposition 15.7 M2/MVIA1 Cu ECP 15.8 Cu CMP,Brief Process Flow - Copper Dual Damascene,Wh

38、y Copper ?,Diffusion barrier SiN,IMD -Via low k Ox,Trench Etching Stop SiN,IMD- Trench Low k Ox,Hard Mask SiN,ARC Lithography SiON,Trench first Via last Etching,Cu Barrier TaN,Cu seed CVD,Cu ECP,Cu CMP,Brief Process Flow - Copper Dual Damascene,Outline,1. Fab flow and Transistor working,2. IC manufa

39、cturing chain,3. Filed application,4. The Trend,wafer processing,2. IC manufacturing chain - Front-end,IDM,Fabless,Turnkey,Fundry,2. IC manufacturing chain - Backend,Assembly and Testing,IDM,System House,IC Design flow,Simulation and Testbility design Level,Design Verification, Physical layout generation ,design optimization,Test pattern generation Level,Tape out , DRC, Mask Tooling and Fab Pilot Level,System Design Entry and Analysis,System Synthesis and Techno