3ov7725参考资料ov7725_datasheet_W

1、OmniisionAdvanced Information Preliminary DatasheetOV7725 Color CMOS VGA (640x480) CAMERACHIPTM Sensorwith OmniPixel2TM TechnologyGeneral DescriptionThe OV7725 CAMERACHIP image sensor is a low voltage CMOS device that provides the full functionality of a single-chip VGA camera and image processor in

2、 a small footprint package. The OV7725 provides full-frame, sub- sampled or windowed 8-bit/10-bit images in a wide range of formats, controlled through the Serial Camera Control Bus (SCCB) interface.This device has an image array capable of operating at up to 60 frames per second (fps) in VGA with c

3、omplete user control over image quality, formatting and output data transfer. All required image processing functions, including exposure control, gamma, white balance, color saturation, hue control and more, are also programmable through the SCCB interface. In addition, OmniVision sensors use propr

4、ietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, blooming, etc., to produce a clean, fully stable color image.ApplicationsCellular and picture phones ToysPC Multimedia Digita

5、l still camerasKey SpecificationsNote: The OV7725 uses a lead-free package.PbFeaturesHigh sensitivity for low-light operation Standard SCCB interfaceOutput support for Raw RGB, RGB (GRB 4:2:2, RGB565/555/444) and YCbCr (4:2:2) formats Supports image sizes: VGA, QVGA, and any size scaling down from C

6、IF to 40x30VarioPixel method for sub-samplingAutomatic image control functions including: Automatic Exposure Control (AEC), AutomaticGain Control (AGC), Automatic White Balance (AWB), Automatic Band Filter (ABF), and AutomaticBlack-Level Calibration (ABLC)Image quality controls including color satur

7、ation, hue, gamma, sharpness (edge enhancement), and anti-bloomingISP includes noise reduction and defect correction Lens shading correctionSaturation level auto adjust (UV adjust) Edge enhancement level auto adjust De-noise level auto adjustFrame synchronization capabilitya.I/O power should be 2.45

8、V or higher when using the internal regulator for Core (1.8V); otherwise, it is necessary to provide an external 1.8V for the Core power supplyFigure 1 OV7725 Pinout (Top View)Ordering Information7725CSP_DS_001 2007 OmniVision Technologies, Inc.Version 1.1, March 30, 2007VarioPixel, OmniVision, and

9、the OmniVision logo are registered trademarks of OmniVision Technologies, Inc. OmniPixel2 and CameraChip are trademarks of OmniVision Technologies, Inc.These specifications are subject to change without notice.ProductPackageOV07725-VL1A (Color, lead-free)28-pin CSP2A1A2A3A4A5A6 ADVDD RSTB VREFH FSIN

10、SCLD0B1B2B3B4B5B6 ADGND VREFN AVDD AGND SDAHREFC1C6PWDNOV7725VSYNCD1D6D5D4E1E2E3E4E5E6 D7D1DVDD PCLK DOVDD D6F1F2F3F4F5F6 D9D3XCLK DOGND D2D8Array Size640 x 480Power SupplyDigital Core1.8VDC + 10%Analog3.0V to 3.3VI/Oa1.7V to 3.3VPower RequirementsActive120 mW typical (60 fps VGA, YUV)Standby 20 ATe

11、mperature Range-20C to +70COutput Format (8-bit) YUV/YCbCr 4:2:2 RGB565/555/444 GRB 4:2:2 Raw RGB DataLens Size1/4Lens Chief Ray Angle25 non linearMax Image Transfer Rate60 fps for VGASensitivity3.0 V/(Lux x sec)S/N Ratio50 dBDynamic Range60 dBScan ModeProgressiveElectronic ExposureUp to 510:1 (for

12、selected fps)Pixel Size6.0 m x 6.0 mDark Current40 mV/sWell Capacity26 Ke-Fixed Pattern Noise 0.03% of VPEAK-TO-PEAKImage Area3984 m x 2952 mPackage Dimensions5345 m x 5265 mOV7725Color CMOS VGA OmniPixel2 CAMERACHIP SensorOmniisionFunctional DescriptionFigure 2 shows the functional block diagram of

13、 the OV7725 image sensor. The OV7725 includes:Image Sensor Array (total array of 656 x 488 pixels, with active pixels 640 x 480 in YUV mode) Analog Signal ProcessorA/D ConvertersTest Pattern GeneratorDigital Signal Processor (DSP) Image ScalerTiming GeneratorDigital Video Port SCCB InterfaceFigure 2

14、Functional Block Diagramcolumn sense ampGbufferbufferanalog processingRA/Dimage arrayBimage scalervideo portDSP*FIFOD9:0exposure/ gain detecttest pattern generatorregistersvideo timing generatorexposure/gain controlSCCBinterfaceclocknote 1 DSP* (lens shading correction, de-noise, white/black pixel c

15、orrection, auto white balance, etc.)7725CSP_DS_0022Proprietary to OmniVision Technologies, Inc.Version 1.1, March 30, 2007row selectXCLKFSIN HREF PCLK VSYNC RSTBPWDNSCLSDAOmniFunctional DescriptionisionImage Sensor ArrayIn general, the combination of the A/D Range Multiplier and A/D Range Control se

16、ts the A/D range and maximum value to allow the user to adjust the final image brightness as a function of the individual application.The OV7725 sensor has an image array of 656 x 488 pixels for a total of 320,128 pixels, of which 640 x 480 pixels are active (307,200 pixels). Figure 3 shows cross-se

17、ction of the image sensor array.aTest Pattern GeneratorFigure 3 Image Sensor ArrayThe Test Pattern Generator features the following:8-bar color bar patternShift 1 in output pinDigital Signal Processor (DSP)This block controls the interpolation from Raw data to RGB and some image quality control.Edge

18、 enhancement (a two-dimensional high pass filter)Color space converter (can change Raw data to RGB or YUV/YCbCr)RGB matrix to eliminate color cross talk Hue and saturation control Programmable gamma controlTransfer 10-bit data to 8-bit7725CSP_DS_003Timing GeneratorIn general, the timing generator co

19、ntrols the following functions:Array control and frame generationInternal timing signal generation and distribution Frame rate timingAutomatic Exposure Control (AEC)External timing outputs (VSYNC, HREF/HSYNC, and PCLK)Image ScalerThis block controls all output and data formatting required prior to s

20、ending the image out. This block scales YUV/RGB output from VGA to CIF and almost any size under CIF.Analog Signal ProcessorThis block performs all analog image functions including:Digital Video PortAutomatic Gain Control (AGC)Automatic White Balance (AWB)Register bits COM21:0 increaseIOL/IOHdrive c

21、urrentand can be adjusted as a function of the customers loading.A/D ConvertersSCCB InterfaceAfter the Analog Processing block, the bayer pattern Raw signal is fed to a 10-bit analog-to-digital (A/D) converter shared by G and BR channels. This A/D converter operates at speeds up to 12 MHz and is ful

22、ly synchronous to the pixel rate (actual conversion rate is related to the frame rate).The Serial Camera Control Bus (SCCB) interface controls the CAMERACHIP sensor operation. Refer to OmniVision Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control por

23、t.In addition to the A/D conversion, this block also has the following functions:Digital Black-Level Calibration (BLC) Optional U/V channel delayAdditional A/D range controlsVersion 1.1, March 30, 2007Proprietary to OmniVision Technologies, Inc.3glassmicrolensmicrolensmicrolensredgreenblueOV7725Colo

24、r CMOS VGA OmniPixel2 CAMERACHIP SensorOmniisionPin DescriptionTable 1Pin Descriptiona.b.c.D9:0 for 10-bit Raw RGB data (D9 MSB, D0 LSB)Input (0) represents an internal pull-down resistor.D9:2 for 8-bit YUV or RGB565/RGB555 (D9 MSB, D2 LSB)4Proprietary to OmniVision Technologies, Inc.Version 1.1, Ma

25、rch 30, 2007Pin NumberNamePin TypeFunction/DescriptionA1ADVDDPowerADC power supplyA2RSTBInputSystem reset input, active lowA3VREFHReferenceReference voltage - connect to ground using a 0.1 F capacitorA4FSINInputFrame synchronize inputA5SCLInputSCCB serial interface clock inputA6D0aOutputData output

26、bit0B1ADGNDPowerADC groundB2VREFNReferenceReference voltage - connect to ground using a 0.1 F capacitorB3AVDDPowerAnalog power supplyB4AGNDPowerAnalog groundB5SDAI/OSCCB serial interface data I/OB6HREFOutputHREF outputC1PWDNInput (0)bPower Down Mode Selection 0: Normal mode1: Power down modeC6VSYNCO

27、utputVertical sync outputD1D5OutputData output bit5D6D4OutputData output bit4E1D7OutputData output bit7E2D1OutputData output bit1E3DVDDPowerPower supply (+1.8 VDC) for digital logic coreE4PCLKOutputPixel clock outputE5DOVDDPowerDigital power supply for I/O (1.7V 3.3V)E6D6OutputData output bit6F1D9cO

28、utputData output bit9F2D3OutputData output bit3F3XCLKInputSystem clock inputF4DOGNDPowerDigital groundF5D2OutputData output bit2F6D8OutputData output bit8OmniElectrical CharacteristicsisionElectrical CharacteristicsTable 2Operating Conditionsa.Exceeding the stresses listed may permanently damage the

29、 device. This is a stress rating only and functional operation of the sensor at these and any other condition above those indicated in this specification is not implied. Exposure to absolute maximum rating conditions for any extended period may affect reliability.Table 3Absolute Maximum RatingsNOTE:

30、Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage.Table 4DC Characteristics (-20C TA 70C)a.At 25C, VDD-A = 3.3V, VDD-C = 1.8V, VDD-IO = 3.3VIDDA = IDD-IO+ IDD-C + IDD-A, fCLK = 24MHz at 30 fps YUV output,

31、no I/O loading IDD-C = 10mA, IDD-A = 8mA, without loadingAt 25C, VDD-A = 3.3V, VDD-C = 1.8V, VDD-IO = 3.3VIDDS-SCCB refers to a SCCB-initiated Standby, while IDDS-PWDN refers to a PWDN pin-initiated Standby Standard Output Loading = 25pF, 1.2K:b.c.d.Version 1.1, March 30, 2007Proprietary to OmniVisi

32、on Technologies, Inc.5SymbolParameterConditionMinTypMaxUnitVDD-ADC supply voltage analog3.03.33.6VVDD-CDC supply voltage digital core1.621.81.98VVDD-IODC supply voltage I/O2.53.3VIDDAActive (operating) currentSee Note a10 + 8bmAIDDS-SCCBStandby currentSee Note c1mAIDDS-PWDNStandby current1020AVIHInp

33、ut voltage HIGHCMOS0.7 x VDD-IOVVILInput voltage LOW0.3 x VDD-IOVVOHOutput voltage HIGHCMOS0.9 x VDD-IOVVOLOutput voltage LOW0.1 x VDD-IOVIOHOutput current HIGHSee Note d8mAIOLOutput current LOW15mAILInput/Output leakageGND to VDD-IO 1AAmbient Storage Temperature-40C to +95CSupply Voltages (with res

34、pect to Ground)VDD-A4.5 VVDD-C3 VVDD-IO4.5 VAll Input/Output Voltages (with respect to Ground)-0.3V to VDD-IO+0.5VLead-free Temperature, Surface-mount process245CParameterMinMaxOperating temperature-20C+70CStorage temperaturea-40C+125COV7725Color CMOS VGA OmniPixel2 CAMERACHIP SensorOmniisionTable 5

35、Functional and AC Characteristics (-20C TA 70C)6Proprietary to OmniVision Technologies, Inc.Version 1.1, March 30, 2007SymbolParameterMinTypMaxUnitFunctional CharacteristicsA/DDifferential non-linearity+ 1/2LSBA/DIntegral non-linearity+ 1LSBAGCRange30dBRed/Blue adjustment range12dBInputs (PWDN, CLK,

36、 RESET#)fCLKInput clock frequency102448MHztCLKInput clock period2142100nstCLK:DCClock duty cycle455055%tS:RESETSetting time after software/hardware reset1mstS:REGSettling time for register change (10 frames required)300msSCCB Timing (see Figure 4)fSCLClock frequency400KHztLOWClock low period1.3stHIG

37、HClock high period600nstAASCL low to data out valid100900nstBUFBus free time before new START1.3stHD:STASTART condition hold time600nstSU:STASTART condition setup time600nstHD:DATData in hold time0stSU:DATData in setup time100nstSU:STOSTOP condition setup time600nstR, tFSCCB rise/fall times300nstDHD

38、ata out hold time50nsOutputs (VSYNC, HREF, PCLK, and D9:0 (see Figure 5, Figure 6, Figure 7, and Figure 8)tPDVPCLKp to data out Valid5nstSUD9:0 setup time15nstHDD9:0 Hold time8nstPHHPCLKp to HREFn05nstPHLPCLKp to HREFp05nsACConditions: VDD:VDD-C = 1.8V, VDD-A = 3.3V, VDD-IO = 3.3V Rise/Fall Times: I

39、/O:5ns, MaximumSCCB: 300ns, Maximum Input Capacitance: 10pf Output Loading: 25pF, 1.2K: to 3.3V fCLK:24MHzOmniTiming SpecificationsisionTiming SpecificationsFigure 4SCCB Timing DiagramtFtHIGHtRSCLtSU:STOtLOWtHD:STAtSU:DATSDA (IN)tSU:STAtAAtBUFSDA (OUT)DH7725CSP_DS_004Figure 5Horizontal TimingtPCLKPC

40、LKtPHLtPHLHREF(rowdata)tSUtPDVD9:0last bytezerofirstbytelast bytetHD7725CSP_DS_005Version 1.1, March 30, 2007Proprietary to OmniVision Technologies, Inc.7ttHD:DATOV7725Color CMOS VGA OmniPixel2 CAMERACHIP SensorOmniisionFigure 6VGA Frame Timing510 x tLINE480 x tLINEVSYNCtLINE = 784 tP8 tLINE144 tPHR

41、EF64 tP37 tP13 tPHSYNCD9:0invalid datainvalid datarow 0row 1P0 - P639row 2row 479note 1 forraw data, tP = tPCLKnote 2 for YUV/RGB, tP = 2 x tPCLK7725CSP_DS_006Figure 7QVGA Frame Timing278 x tLINE1240 x tLINEVSYNCtLINE = 576 tP12 tLINE256 tPHREF64 tP149 tP43 tPHSYNCD9:0invalid datainvalid datarow 1P0

42、 - P319row 0row 2row 239note 1 for raw data, tP = tPCLKnote 2 for YUV/RGB, tP = 2 x tPCLK7725CSP_DS_007Figure 8CIF Frame TimingVGA HREF(see figure 6, VGA frame timing)CIFHREF(3 from 5)VSYNC7725CSP_DS_0088Proprietary to OmniVision Technologies, Inc.Version 1.1, March 30, 2007320 tP4 x tLINE22 tLINE64

43、0 tP4 x tLINE18 tLINEOmniTiming SpecificationsisionFigure 9RGB 565 Output Timing DiagramtPCLKPCLKtPHLtPHLHREF(rowdata)tPDVtSUD9:2last bytezerofirst bytelast bytetfir t bytesecondD9D8D7D9D8D7D6D5D6D5D4D3D2D4D3D27725CSP_DS_009Figure 10RGB 555 Output Timing DiagramtPCLKPCLKtPHLtPHLHREF(rowdata)tPDVtSUD

44、9:2last bytezerofirst bytelast bytetfir t bytesecondD9D8D7D6D5D4D3D2D9D8D7D6D5D4D3D27725CSP_DS_010Version 1.1, March 30, 2007Proprietary to OmniVision Technologies, Inc.9. B0XR4. R0G4G3HDbyteG2. G0B4. B0R4. R0G5. G3HDbyteG2. G0B4OV7725Color CMOS VGA OmniPixel2 CAMERACHIP SensorOmniisionFigure 11RGB

45、444 Output Timing DiagramtPCLKPCLKtPHLtPHLHREF(rowdata)tPDVtSUD9:2last bytezerofirst bytelast bytetHDfirsecond byteD9D8D7D6D5D4D3D2D9D8D7D6D5D4D3D2G3. G0B3. B07725CSP_DS_01110Proprietary to OmniVision Technologies, Inc.Version 1.1, March 30, 2007t byteX. XR3. R0OmniRegister SetisionRegister SetTable

46、 6 provides a list and description of the Device Control registers contained in the OV7725. For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 42 for write and 43 for read.Table 6Device Control Register List (Sheet 1 of 13)Version 1.1, March 30, 2007Prop

47、rietary to OmniVision Technologies, Inc.11Address (Hex)Register NameDefault (Hex)R/WDescription00GAIN00RWAGC Gain control gain setting Bit7:0: AGC7:0 Range: 00 to FF01BLUE80RWAWB Blue channel gain setting Range: 00 to FF02RED80RWAWB Red channel gain setting Range: 00 to FF03GREEN00RWAWB Green channe

48、l gain setting Range: 00 to FF04RSVDXXReserved05BAVG00RWU/B Average LevelAutomatically updated based on chip output format06GAVG00RWY/Gb Average LevelAutomatically updated based on chip output format07RAVG00RWV/R Average LevelAutomatically updated based on chip output format08AECH00RWExposure Value AEC MSBsBit7:0: AEC15:8 (see register A